Question: Short note on Programmable peripheral interface 8255 need for and operation in Mode 1.
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Mumbai university > Electronics engineering > Sem 4 > MPP Marks : 5 Year : may 2018

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modified 9 weeks ago  • written 9 weeks ago by gravatar for Ankit Pandey Ankit Pandey ♦♦ 10
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The 8255 is a general purpose programmable I/O device designed to transfer the data from I/O to interrupt I/O under certain conditions as required. It can be used with almost any microprocessor.

It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be configured as per the requirement.

Features of IC 8255:-

  1. It consists of 3, 8-bit IO ports i.e. Port A, Port B, and Port C.
  2. Address/data bus must be externally demux'd.
  3. It is TTL compatible.
  4. It has improved DC driving capability.
  5. Fully compatible with Intel microprocessor family.
  6. Direct bit set/reset capability is available for port C.
  7. It can be operate in 3 modes:-

a) Mode 0-simple I/O

b) Mode 1-strobed I/O

c) Mode 2-strobed bi-directional I/O

The block diagram of 8255 is as shown in fig.

enter image description here

It contains following blocks:

  1. Data bus buffer

  2. Read/write control logic

  3. Group A and group B control

  4. Port A and port B

  5. Port C

Data bus buffer:-

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control words and status information is also transferred using this bus. The direction of data buffer is decided by read and write control signals. When read is activated, it transmits data to the system data bus. When write is activated, it receives data from system data bus.

Read/write control logic:-

This block is responsible for controlling the internal/external transfer of data/control/status word. It accepts the input from the CPU address and control buses, and in turn issues command to both the control groups.

(CS) Chip Select. A "low" on this input pin enables the communcation between the 8255 and the CPU.

(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.

(WR) Write. A "low" on this input pin enables the CPU to write data or control words into the 8255.

Group A and group B control:-

  1. Group A consisting of port A and upper part of port C.
  2. Group B consisting of port B and lower part of port C.
  3. Each group is programmed through software.
  4. The bit pattern is given by CPU consists of information

    a)To control the operation of group A and group B

    b) The mode in which they should be operated.

Port A and port B:-

Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-down" bus-hold devices are present on Port A.

Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.

Port C:-

One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.

8255 operating modes:-

  1. The 8255 IC provides one control word register.
  2. It is selected when A0=1,A1=1,CS =0 and WR=0.The read operation is not allowed for control register.
  3. The bit pattern loaded in control word register specifies an I/O function for each port and the mode of operation in which the ports are to be used.
  4. There are two different control word formats which specify two basic modes:
  • BSR (Bit set reset) mode

  • I/O mode

  1. The two basic modes are selected by D7D7 bit of control register. When D7=1D7=1 it is an I/O mode and when D7=0D7=0; it is a BSR mode.

BSR mode:-

enter image description here

  1. The BSR mode is a port C bit set/reset mode.
  2. The individual bit of port C can be set or reset by writing control word in the control register.
  3. The control word format of BSR mode is as shown in the fig.
  4. The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit S/R ̅.
  5. The BSR mode affects only one bit of port C at a time. 6.0The bit set using BSR mode remains set unless and until you change the bit. So to set any bit of port C, bit pattern is loaded in control register.
  6. If a BSR mode is selected it will not affect I/O mode. I/O modes-

There are three I/O modes of operation:

• Mode 0- Basic I/O

• Mode 1- Strobed I/O

• Mode 2- Bi-directional I/O

The I/O modes are programmed using control register.

The control word format of I/O modes is as shown in the figure below:

enter image description here

Function of each bit is as follows:

  1. D7 – When the bit D7 = 1 then I/O mode is selected, if D7=0 then BSR mode is selected. The function of bits D0 to D6 is independent on mode (I/O mode or BSR mode).
  2. D6 and D5 – In I/O mode the bits D6 and D5 specifies the different I/O modes for group A i.e. Mode 0, Mode 1 and Mode 2 for port A and port C upper.
  3. D4 and D3 – In I/O mode the bits D4 and D3 selects the port function for group A. If these bits = 1 the respective port specified is used as input port. But if bit =0, the port is used as output port.
  4. D2 – In I/O mode the bit D2 specifies the different I/O modes for group B i.e. Mode 0 and Mode 1 for port B and port C lower.
  5. D1 and D0 – In I/O mode the bits D1 and D0 selects the port function for group B. If these bits = 1 the respective port specified is used as input port. But if bit = 0, the port is used as output port.

All the 3 modes i.e. Mode 0, Mode 1 and Mode 2 are only for group A ports, but for group B only 2 modes i.e. Mode 0 and Mode 1 are provided. When 8255 is reset, it will clear control word register contents and all the ports are set to input mode. The ports of 8255 can be programmed for other modes by sending appropriate bit pattern to control register.

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written 9 weeks ago by gravatar for Ankit Pandey Ankit Pandey ♦♦ 10
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