VLSI Design Question Paper - May 17 - Electronics Engineering (Semester 6)

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VLSI Design - May 17

Electronics Engineering (Semester 6)

TAKEN FROM CREDIT BASED PATTERN

Total marks: 80
Total time: 3 Hours INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Q.1. Solve Any 4

1.a. Compare NMOS & CMOS technology in VLSI design.

(5 marks) 8548

1.b. Implement the following function using Dynamic CMOS logic.

$Y=\overline{(A(B+C))}$

(5 marks) 8564

1.c. Compare Ripple carry adder with CLA.

(5 marks) 8586

1.d. Explain working principle of flash memory.

(5 marks) 8577

1.e. Explain importance of low power design.

(5 marks) 8600

2.a. Compare the full scaling and constant voltage scaling models of MOSFET.Demonstrate the effects of scaling on the area,delay,power consumption and current density of the device.

(10 marks) 8549

2.b. Explain transfer characteristic for NMOS.Inverter Showing different regions.What is the effect of variation in W/L ratio?

(10 marks) 8556

3.a. Draw 1T DRAM Cell and explains it's write,read,hold and refresh operation.

(10 marks) 8579

3.b. Explain Scheme of multiplication $101*010$

(10 marks) 8587

4.a. Explain various techniques of clock generation and clock distribution.

(10 marks) 8596

4.b. Consider a CMOS inverter circuit with following parameters.

$V_{DD} =3.3 V, V_{To,n} = 0.6 V, V_{To,p} = -0. 7V, K_n = 200 \mu A/V^2, K_p = 80 \mu A/V^2$

Calculate noise margins of the circuit Consider $K_R = 2.5$ and $V_{To,n} \neq V_{To,p}$

(10 marks) 8558

5.a. Draw JK Flip Flop using CMOS and explain the working.

(10 marks) 8565

5.b. Draw CLA (carry lookahead adder) carry chain using dynamic CMOS logic.

(10 marks) 8589

Q.6. Write Short notes on (Any three)

6.a. LATCH UP in CMOS

(7 marks) 12268

6.b. Sense Amplifier

(7 marks) 8585

6.c. Interconnect Scaling

(6 marks) 8550

6.d. $4*4 Barrel \ Shifter$

(6 marks) 8591

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