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VLSI Design Question Paper - Dec 18 - Electronics Engineering (Semester 6) - Mumbai University (MU)
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VLSI Design - Dec 18

Electronics Engineering (Semester 6)

TAKEN FROM CREDIT BASED PATTERN

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Q.1. Solve Any 4

1.a. Compare Biploar,NMOS and CMOS technologies (min three points)
(5 marks) 8548

1.b. Design a 2:1 MUX using transmission gates and discuss advantages of use of transmission gate logic.
(5 marks) 8560

1.c. Implement $Y=\overline{(A.B)+ (C.D)}$ using Dynamic Logic.
(5 marks) 8561

1.d. Compare Ram and ROM.
(5 marks) 8574

1.e. Explain clock generation techniques.
(5 marks) 8596

2.a. Sketch and explain the general shape of the Transfer characteristics of NMOS inverter.Compare different types of inverters.
(10 marks) 8555

2.b. Compare the full scaling model with constant voltage scaling model for MOSFETS. Demonstrate clearly the effects of scaling on the device density, speed of the circuit, power consumption and current density of the gates
(10 marks) 8549

3.a. Implement D flip-flop using Static CMOS. What are other design methods for it?
(10 marks) 8562

3.b. Explain READ and WRITE operation of 6-T SRAM cell in detail.
(10 marks) 8575

4.a. What is ESD protection? Explain with example.
(10 marks) 8597

4.b. Explain Carry Look Ahead adder and it’s advantages.
(10 marks) 8589

5.a. What are different clock distribution schemes? Explain concept of Global and Local clock.
(10 marks) 8598

5.b. What are various decoders used in memory structures? Explain any one in detail.
(10 marks) 8576

Q.6. Write Short note on (Any 3)

6.a. NORA ,Zipper Logic design
(7 marks) 8563

6.b. Flash Memory
(7 marks) 8577

6.c. CMOS latch-up and its prevention
(6 marks) 8599

6.d. Sense Amplifier,
(6 marks) 8585

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