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Digital System Design Question Paper - Dec 17 - Electronics And Telecomm (Semester 3) - Mumbai University (MU)
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Digital System Design - Dec 17
Electronics And Telecomm (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1.a.
Explain the following decimals in gray code form
(5 marks)
00
i. $(42)_{10}$
ii. $(17)_{10}$
1.b.
Explain Mealy machine and Moore machine
(5 marks)
00
1.c.
Design a full adder using 3:8 Decoder
(5 marks)
00
1.d.
Convert JK flip flop to T flip flop
(5 marks)
00
2.a.
Prove that NAND and NOR gates are Universal gates
(10 marks)
00
2.b.
Implement the following Boolean function using 8:1 multiplexer.
$F(A,B,C,D)=\sum M(0,1,4,5,6,8,10,12,13)$
(10 marks)
00
3.a.
Explain the Johnson's Counter. Design for initial state 0110. From initial state explain and draw all possible states
(10 marks)
00
3.b.
Minimize the following expression using Quine Mc-cluskey technique.
(10 marks)
00
$F(A,B,C,D) = \sum M(0,1,2,3,5,7,9,11)$
4.a.
Design a 2 bit comparator and implement using logic gates
(10 marks)
00
4.b.
Using Boolean Algebra Prove the following
(10 marks)
00
i. $AB+BC+\bar AC=AB+ \bar AC$
ii.$[(C+ \bar CD)(C+ \bar C \bar D][AB+ \bar A \bar B+(A \ XOR \ B)]=C$
5.a.
Explain the working of 3 bit asynchronous counter with proper timing diagram
(10 marks)
00
5.b.
What is shift register? Explain any one type of shift register. Give its applications.
(10 marks)
00
6.a.
VHDL Code for Full Subtractor
(5 marks)
00
6.b.
Explain CPLD and FPGA
(5 marks)
00
6.c.
Explain SRAM and DRAM.
(5 marks)
00
6.d.
Compare TTL and CMOS logic families
(5 marks)
00
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