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Digital Circuit Design Question Paper - Dec 16 - Electronics Engineering (Semester 3) - Mumbai University (MU)
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Digital Circuit Design - Dec 16

Electronics Engineering (Semester 3)

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Solve any Four

1.a. Write the truth table of half adder and write a VHDL code for half adder.
(5 marks) 00

1.b. Explain advantages of JTAG architecture.
(5 marks) 00

1.c. Explain advantages and drawback of synchronous counter.
(5 marks) 00

1.d. Explain the following terms:

  1. Noise margin

  2. Noise immunity

  3. Propagation delay with reference to digital ICs

(5 marks) 00

1.e. Differentiate between multiplexer and demultiplexer.
(5 marks) 00

2.a. Design a Meal type sequence detector to detect three or more consecutive 1's in a string of bits coming through an input line.
(10 marks) 00

2.b. What are universal gates? Why are they called so? Implement XOR and XNOR function using all NAND gates.
(10 marks) 00

3.a. enter image description here

Analyze the sequential state machine shown in figure and obtain state diagram for the same.

(5 marks) 00

3.b. Obtain excitation table for JK flip flop and convert JK flip flop to T flip flop.
(10 marks) 00

4.a. Draw a circuit diagram of 2 input TTL NAND gate and Explain the interfacing of TTL and CMOS.
(10 marks) 00

4.b. Design a MOD 10 asynchronous counter using T flip flop.
(10 marks) 00

5.a. Design a combinational circuit using a suitable PAL considering the following Boolean expressions. Use a PAL with four inputs and four outputs and three wide AND OR structure.

$W(a,b,c,d) = \Sigma m(2,12,13)$

$X(a,b,c,d,) = \Sigma m(7,8,9,10,11,12,13,14,15)$

(10 marks) 00

5.b. Design 4 bit Johnson counter using J-K flip flop. Explain its working using waveform
(10 marks) 00

Write short notes on:

6.a. Stuck at zero and stuck at 1 fault.
(5 marks) 00

6.b. Entity declaration and architecture declaration.
(5 marks) 00

6.c. FPGA architecture.
(5 marks) 00

6.d. State reduction and state assignment.
(5 marks) 00

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