Digital Circuit Design Question Paper - May 17 - Electronics Engineering (Semester 3)

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Digital Circuit Design - May 17

Electronics Engineering (Semester 3)

Total marks: 80
Total time: 3 Hours INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

1.a. Two inputs TTL NAND gate

(5 marks) 00

1.b. Explain ring counter.

(5 marks) 00

1.c. Draw truth table and logic diagram of Full Subtractor using half Subtractors and gates.

(5 marks) 00

1.d. Explain the characteristics parameters of logic families.

(5 marks) 00

2.a. Analyse the clocked synchronous machine given below. Write excitation equations, excitation/transition table and state output table (Use state names A-D for Q1-Q-2 =00-11)

enter image description here

(10 marks) 00

2.b. Design 1 digit BCD adder using IC 7483 and perform $(1010)_{BCD} +(1100)_{BCD}$

(10 marks) 00

3.a. Design a mealy sequence detector to detect----0100---- using D flip flops and logic gates

(10 marks) 00

3.b. Design a circuit with optimum utilization of PLA to implement the following functions

$P = \Sigma m (1,3,8,10,10,15)$

$Q = \Sigma m (0,1,5,7,9,12,14)$

$R = \Sigma m (0,2,5,8,9,11)$

(10 marks) 00

4.a. Implement following functions using 4:1 MUX and NAND gates.

$P(A,B,C,D) = \Sigma m(1,2,6,7,8,10,13,14)$

(10 marks) 00

4.b. Explain IC 74194 working in detail with applications.

(10 marks) 00

5.a. Use K-map to reduce following function and then implement it by NOR gates.

$F = \pi M(0,1,4,7,8,11,12,14) +d(2,5,6)$

(10 marks) 00

5.b. Eliminate the redundant states and draw the reduced state diagram

enter image description here

(10 marks) 00

Write short notes on(Any Three):

6.a. Master slave JK Flip Flop

(10 marks) 00

6.b.
Write a VHDL code for full adder

(10 marks) 00

6.c
Stuck at '0'and '1' faults

(10 marks) 00

6.d.
CPLD and FPGA architecture block diagram

(10 marks) 00

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