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Digital Logic Design And Analysis Question Paper - Dec 18 - Computer Engineering (Semester 3) - Mumbai University (MU)
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Digital Logic Design And Analysis - Dec 18
Computer Engineering (Semester 3)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1.a.
Convert decimal number 576.24 into binary, base-9,Octal, hexadecimal system.
(4 marks)
00
1.b.
Construct hamming code for 1010 using odd parity.
(4 marks)
00
1.c.
Convert $(-89)_{10}$ to its equivalent Sign Magnitude, 1's complement and 2's Complement Form.
(4 marks)
00
1.d.
Perform$(BC5)_{H}$ - $(A2B)_{H}$ without converting to any other base
(4 marks)
00
1.e.
Prove De Morgans theorem
(4 marks)
00
2.a.
Given the logic expression : $A + \bar B \bar C + AB\bar D + ABCD $
(10 marks)
00
Express it in standard SOP form.
Draw K-map and simplify.
Draw logic diagram using NOR gates only.
2.b.
Reduce using Quine McClusky method and realise the operations using only NAND gates.
$F(A,B,C,D) = \amalg M(0,2,3,6,7,8,9,12,13)$
(10 marks)
00
3.a.
Design a 4-bit binary to gray code converter.
(10 marks)
00
3.b.
Design a 4-bit BCD adder using IC 7483 and necessary gates.
(10 marks)
00
4.a.
Implement the following logic function using all 4:1 multiplexers with the select inputs as 'B','C','D','E' only.
$ F(A,B,C,D,E) = \Large \Sigma m (0,1,2,3,6,8,9,10,13,15,17,20,24,30)$
(10 marks)
00
4.b.
Convert a SR flip-flop to JK flip-flop.
(10 marks)
00
5.a.
Design a mod-6 synchronous counter using T FF.
(10 marks)
00
5.b.
Explain the operation of 4-bit universal shift register.
(10 marks)
00
Write short notes on any two
6.a.
VHDL
(10 marks)
00
6.b.
TTL and CMOS logic families
(10 marks)
00
6.c.
4-bit Magnitude compartor.
(10 marks)
00
6.d.
3 to 8 line decoder.
(10 marks)
00
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