Question Paper: Logic Design : Question Paper Jun 2015 - Electronics & Communication (Semester 3) | Visveswaraya Technological University (VTU)
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Logic Design - Jun 2015

Electronics & Communication (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
1 (a) Express the following Boolean function in canonical max term form:
F(A, B, C)= AB+C.
(4 marks)
1 (b) Express the following Boolean function in canonical term form:
F(A, B, C, D)=AB+CD.
(8 marks)
1 (c) Simplify the following Boolean function using four variable 'k' map. Realize the simplified expression using NAND gates.
F(A, B, C, D)= ∑m(1, 5, 6, 7, 11, 12, 13, 15).
(8 marks)
2 (a) Simplify the following Boolean function using Quine-McClusky's minimization technique.
F(A, B, C, D)= ∑m(6, 7, 9, 10, 13) + d(1, 4, 5, 11, 15).
(10 marks)
2 (b) Consider the following Boolean equation:
F(A, B, C, D) = ∑m(1, 3, 7, 11, 15) + ∑d(0, 2, 5).
Simplfy the function F using a 3 variable MEV k-map. Assign the variable D to be the MEV.
(10 marks)
3 (a) Implement the Boolean functions:
F1(x,y,z)=XY+YZ
F2(x,y,z)=πm(0, 3, 5)
Using a 3-8 line decoder IC 74138 with active low outputs.
(8 marks)
3 (b) Interface a 10 key keypad to a digital system using a IC 74147 which is a 10 line to BCD priority encoder. Draw the logic diagram and explain the operation with the truth table.(12 marks) 4 (a) Implement the Boolean function:
F(A, B,C, D)=∑m (0, 1, 2, 4, 5, 7, 8, 9)
Using a 8 to 1 multiplexer. Draw the logic diagram and explain the operation. Additional gates can be used if required.
(8 marks)
4 (b) Explain the operation of a full subtractor with the help of a truth table and Boolean expression for the outputs. Implement the full subtractor using two number of
i) 4 to 1 multiplexers
ii) 2 to 1 multiplexers.
Additional gates if required can be used.
(8 marks)
4 (c) Design a one bit binary comparator.(4 marks) 5 (a) Explain the operation of a gated SR latch with a logic diagram and a truth table.(6 marks) 5 (b) Explain the operation of a positive edge trigged 'D' flip-flop with the help of a logic diagram and truth table. Also draw the relevant waveforms.(4 marks) 5 (c) Draw the output waveforms QM and QS the outputs of the master and the slave respectively, if the inputs to a master slave JK flip-flop one as indicated below.
:!MAGE-
(10 marks)
6 (a) Design a 4 bit binary ripple up counter using negative edge triggered JK flip-flops. Draw the timing diagram with respect to the input cock pulse. Explain the operation.(10 marks) 6 (b) Design a synchronous counter using clocked JK flip-flop for the counting sequence shown below:

Q2 Q1 Q0
0 0 0
0 1 0
0 1 1
1 1 0
1 0 1
0 0 1
0 0 0
(10 marks) 7 (a) Explain mealy and Moore models of a clocked synchronous sequential circuit.(8 marks) 7 (b) Design a synchronous circuit using positive edge triggered JK flip-flop to generate the following sequence:
0-1-2-0 is input x=0 and
0-2-1-0 is input x=1
Provide an output which goes high to indicate the non-zero state in the 0-1-2-0 sequence.
(12 marks)
8 Construct the excitation table, transition table, state table and state diagram for the sequential circuit shown in Fig. Q8
:!MAGE-
(20 marks)

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