Fundamentals of HDL - Dec 2014
Electronics & Communication (Semester 4)
TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks. 1 (a) Explain the behavioural and dataflow style descriptions of VHDL, with the example of an half-adder.(10 marks) 1 (b) Compare VHDL and verilog.(4 marks) 1 (c) Explain structure of VHDL and verilog with an example.(6 marks) 2 (a) Write VHDL code for 2×2 bits combinational array multiplier (Dataflow style description).(6 marks) 2 (b) List the data types used in VHDL and verilog.(4 marks) 2 (c) Write a dataflow description in both VHDL and verilog, for u full adder with active high enable (en=1).(10 marks) 3 (a) Distinguish between signal assignment and variable assignment statement in VHDL. Also, write VHDL; program for behavioural description of D-latch using assignment and variable assignment statements, separately.(10 marks) 3 (b) Explain formats of for loop and while loop statements in both VHDL and verilog.(6 marks) 3 (c) Write VHDL code to calculate the factorial of positive integers.(4 marks) 4 (a) Write the structural description for full adder, using two half adders.(6 marks) 4 (b) Explain binding between two modules in verilog.(4 marks) 4 (c) Write VHDL structural description of 3-bits synchronous up counter using JK master slave flip flops.(10 marks) 5 (a) Give an example code for a procedure and a function.(6 marks) 5 (b) Write VHDL description of a full adder using procedure.(8 marks) 5 (c) Write a verilog code for converting a fraction binary to real using task.(6 marks) 6 (a) Why a mixed typed description is needed? Write the VHDL code to find largest element in an array.(10 marks) 6 (b) Write a note on package in VHDL.(3 marks) 6 (c) Write VHDL code for the addition of 5× 5 matrices using a package.(7 marks) 7 (a) With a mixed language description of a full adder, explain the invoking of VHDL entity from a verilog module.(10 marks) 7 (b) Write the mixed language description of a JK master-slave flip-flop with clear input.(10 marks) 8 (a) What is meant by synthesis? List and explain steps involved in synthesis.(7 marks) 8 (b) Write VHDL or verilog code for the signal assignment statement y=2×a+5 for an entity with one input a of 3-bits and one output y of 4-bits. Show the mapping of this signal assignment to gate level.(10 marks) 8 (c) Explain extraction of synthesis information from an entity.(3 marks)