## Digital Electronics and Logic Design - Dec 2013

### Computer Engg (Semester 3)

TOTAL MARKS: 100

TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.

(2) Attempt any **four** from the remaining questions.

(3) Assume data wherever required.

(4) Figures to the right indicate full marks.

### Answer any one question from Q1 and Q2

**1 (a)** Minimize the following function using K-map & realize using Logic gates.

F(A,B,C,D) = ∑m(1,3,7,11,15) + d(0,2,5)(4 marks)
**1 (b)** Converting following:

(255)_{10}=(?)_{16}(2 marks)
**1 (c)** Differentiate between standard TTL and CMOS logic circuit w.r.t.

i) Propagation delay

ii) FANOUT

iii) Figure of merit(6 marks)
**2 (a)** Convert the following numbers into binary and hexadecimal numbers.

i) (46)_{8} ii) (20.5)_{10}(4 marks)
**2 (b)** Define the following terms and mention its standard values for TTL family.

i) Voltage and Current parameter.

ii) Power Dissipation.

iii) Noise margin.(6 marks)
**2 (c)** Represent the following signed number in 2's complement method:

i) +8 ii) -8(2 marks)

### Answer any one question from Q3 and Q4

**3 (a)** Design a 4-bit BCD to Excess-3 code converter circuit using minimum number of logic gates.(6 marks)
**3 (b)** Design Mod-5 synchronous counter using JK flipflops.(4 marks)
**3 (c)** Draw the excitation table of S-R Flip-flop.(2 marks)
**4 (a)** Design a 3-bit binary to 3-bit gray code converter using IC-74138.(4 marks)
**4 (b)** How many Flip-flops are required to build a binary counter circuit to count from 0 to 2048. What is the frequency of the output of last Flip-flop for an input clock frequency of 6MHz?(6 marks)
**4 (c)** Perform the following:

(1111)_{2} + (1111)_{2}=?(2 marks)

### Answer any one question from Q5 and Q6

**5 (a)** State and explain basic component of ASM chart? What is difference between ASM chart and conventional flow chart?(7 marks)
**5 (b)** Write VHDL code 8:1 Multiplexer using Behavioural and Dataflow modelling style.(6 marks)
**6 (a)** Design a sequence generator circuit to generate the sequence 1-3-5-7 using Multiplexer Controller based ASM approach.

Consideration:

i) If control input C = 0, the sequence generator circuit in the same state.

ii) If control input C = 1, the sequence generator circuit goes into next state.(7 marks)
**6 (b)** Explain the following statements used in VHDL with suitable examples:

i) Process.

ii) CASE.

iii) With-Select-When.(6 marks)

### Answer any one question from Q7 and Q8

**7 (a)** What are different types of PLDs? Design 3:8 decoder using PLD.(7 marks)
**7 (b)** Draw and explain the basic architecture of FPGA.(6 marks)
**8 (a)** A combinational circuits is defined by the function

F_{1} (A,B,C)= ∑m(0,1,2,4)

F_{2} (A,B,C)= ∑m(1,3,5,6)

Implement this circuit with PLA.(7 marks)
**8 (b)** A combinational circuits is defined by the function

F 1 (A,B,C)= ∑m(0,1,3,4)

Implement this circuit with PAL.(6 marks)