Question Paper: Digital Electronics and Logic Design : Question Paper Jun 2015 - Computer Engineering (Semester 3) | Pune University (PU)
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Digital Electronics and Logic Design - Jun 2015

Computer Engineering (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.


Answer any one question from Q1 and Q2

1 (a) Minimize the following function using K-map and realize using logic gates: F(A, B, C, D) = ∑m (1, 5, 7, 13, 15) + d(0, 6, 12, 14)(4 marks) 1 (b) Convert the following: (46)10=(?)8(2 marks) 1 (c) List the differences between CMOS and TTL.(6 marks) 2 (a) Convert the following numbers into binary numbers?
i) (37)8
ii) (25.5)10
(4 marks)
2 (b) Explain standard TTL characteristics in detail.(6 marks) 2 (c) Represent the following signed number in 2's complement method:
i) +25 ii) -25
(2 marks)


Answer any one question from Q3 and Q4

3 (a) Design a 3-bit excess 3 to 3-bit BCD code converter using logic gate.(6 marks) 3 (b) Design mod-5 synchronous counter using J-K flip-flop.(4 marks) 3 (c) Draw the excitation table of J-K Flip-flop.(2 marks) 4 (a) Design a 4-bit binary to Gray code converter circuit using logic gates.(4 marks) 4 (b) Design a Mod 20 counter using decade counter IC7490.(6 marks) 4 (c) Perform the following:
(11011)2 + (0101)2 = (?)2.
(2 marks)


Answer any one question from Q5 and Q6

5 (a) State and explain basic component of ASM chart ? Also explain the salient features of ASM chart.(7 marks) 5 (b) Write VHDL code 4:1 multiplexer using behavioural and data flow modelling style.(6 marks) 6 (a) Design a sequence generator circuit to generate the sequence 1?2?3?7?1 using Multiplexer controller based ASM approach. Consideration:
(i) If control input C = 0, the sequence generator circuit in the same state.
(ii) If control input C = 1, the sequence generator circuit goes into next state.
(7 marks)
6 (b) Explain the following statements used in VHDL with suitable Examples:
(i) CASE
(ii) With select-when
(iii) Loop statement.
(6 marks)


Answer any one question from Q7 and Q8

7 (a) Comparison between PROM, PLA and PAL.(7 marks) 7 (b) Draw and explain the basic architecture of FPGA.(6 marks) 8 (a) A combinational circuits is defined by the function:
F1 (A, B, C) = ∑m (0, 1, 3, 7)
F2 (A, B, C) = ∑m (1, 2, 5, 6)
Implement this circuit with PLA.
(7 marks)
8 (b) A combinational circuits is defined by the function:
F1 (A, B, C) = ∑m (0, 1, 5, 6, 7)
Implement this circuit with PAL.
(6 marks)

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