Question Paper: Digital Electronics : Question Paper Jun 2015 - Electronics & Telecom Engineering (Semester 3) | Pune University (PU)
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Digital Electronics - Jun 2015

Electronics & Telecom Engineering (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.


Answer any one question from Q1 and Q2

1 (a) Draw and explain the working of two input TTL NAND gates (with totem pole).(6 marks) 1 (b) Implement the following function using single 8 : 1 MUX.
F(A, B, C, D) = ∑m (1, 4, 6, 8, 10, 11, 13, 14)
(6 marks)
2 (a) Design and implement full adder using suitable decoder.(6 marks) 2 (b) Draw and explain the working of 2 i/p CMOS NOR gate.(6 marks)


Answer any one question from Q3 and Q4

3 (a) Design mod 6 ripple up counter using T flip-flops.(6 marks) 3 (b) Convert D to T and vice versa.(6 marks) 4 (a) Explain Moore circuit with example. Also compare Moore and Mealy circuit.(6 marks) 4 (b) Design a sequence detector to detect sequence 1101 using D FF and mealy machine.(6 marks)


Answer any one question from Q5 and Q6

5 (a) Compare between PROM and PAL.(5 marks) 5 (b) A combinational circuit is defined by a function F1 = ∑m(1, 3, 5) F2= ∑m (5, ,6, 7).
Implement the circuit with PLA having 3 inputs, 3 product terms and two outputs.
(8 marks)
6 (a) Explain in detail the architecture of CPLD.(6 marks) 6 (b) What is meant by EPROM ? State its advantages and disadvantages.(7 marks)


Answer any one question from Q7 and Q8

7 (a) Explain the following statements with examples:
i) Process
ii) Case
iii) If else.
(6 marks)
7 (b) Write a VHDL code for 8:1 multiplexer using behavioural modelling.(7 marks) 8 (a) Explain in detail signal and variable with example in VHDL.(6 marks) 8 (b) Write a VHDL code for 4-bit ALU using case statement.(7 marks)

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