**PLL as Frequency Synthesizer:**

The block diagram of PLL as frequency synthesizer is as shown in fig. 10. Note that this circuit is same as the frequency multiplier circuit except for the divide by M network added as shown in Fig.10.

**Operation:**

The frequency synthesizer is supposed to produce an output an output signal, the frequency of which can be precisely adjusted to any value in a prescribed range. The output frequencies of a synthesizer should be very stable. In order to ensure the stability of output frequency, crystal oscillator of frequency $f_{osc}$ is used. The output frequency of crystal oscillator is divided by M with the help of the divide by M network. Thus the input frequency to PLL is $(f_{osc} /M)$ as shown in fig. 10

The PLL will compare this frequency with the frequency at the output of divide by N network, and will try to adjust this frequency equal to $\frac{f_{osc}}{M}$. In order to obtain the same frequency i.e $(\frac{f_{osc}}{/m})$ at the output of divide by N network, the VCO frequency should be adjusted to,

$f_{VCD} = \frac{f_{OSC}}{M} \times N \hspace{2cm} .......... (1)$

OR

$f_{VCD} = (\frac{N}{M}) f_{OSC} \hspace{2cm} .......... (2)$

in what year's question paper was this question?

190