Integrated Circuits : Question Paper May 2012 - Electronics & Telecomm. (Semester 5) | Mumbai University (MU)

Integrated Circuits - May 2012

Electronics & Telecomm. (Semester 5)

(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks.
1 (a) Design a circuit with Op-Amp, resistors and a capacitor that simulates an inductor of 1 H.(5 marks) 1 (b) Design an Op-Amp circuit that simulates the relation V0=2V1+5V2 with the minimum number of resistors and Op Amps(5 marks) 1 (c) Draw a sample and hold circuit with buffers: Bi at the input side and Bo at the output side. Write down the requirements (very high or very low) regarding the rise time, bias current, input impedance and the output impedance for the two buffers and justify (5 marks) 1 (d) Differentiate between static and dynamic RAMs.(5 marks) 2 (a) Draw the circuit of a voltage to current converter (VCC) for a grounded load and derive the condition for it to acts as a VCC. Design a VCC that has a trans-conductance of I mA/V. how VCC can be used to generate a triangular wave from a square wave.(10 marks) 2 (b) (i) What are the functions of the 'control pin' and the 'discharge transistor' in the astable mode of operation of timer 555?(2 marks) 2 (b) (ii) Draw the circuit for IC 8038 operating as an astable multi-vibrator with 50% duty cycle. Derive a relation for the frequency of the square wave. Design the circuit for a frequency of 20 kHz(8 marks) 3 (a) (i) Draw a general circuit for a multiple feedback filter. Obtain its voltage transfer function (in terms of various admittances). From the transfer function, identify the elements (registors and capacitors) for a band pass filter(8 marks) 3 (a) (ii) Design a band pass filter for a central frequency of 1 kHz and Band width of 200 Hz(4 marks) 3 (a) (iii) How can the gain at the centre frequency be reduced by 50 % using only one extra resistance? Modify the above band pass filter to obtain a band reject filter(8 marks) 4 (a) Give a circuit for simulating a resistor using a switched capacitor. Derive the relation for the simulation resistance. What are the requirements form the ideal switch, the capacitor and the clock frequency?(12 marks) 4 (b) An inverting type Schmitt trigger has the following transfer characteristics: Threshold levels are 5V and -6 V, output voltage ∓10 V. plot the output voltage when the inpur voltages are
(i) 8 sin 10t,
(ii) Positive half-wave rectified 8 sin 10t
(8 marks)
5 (a) (i) Compare the R-2R ladder (voltage mode) and weight resistor DACs under the following heads. Number of resistors, spread Number of single-pole single-thorw switches and the Speed of operation(4 marks) 5 (a) (ii) Draw the current mode R-2R digital to analog converter. Why is it suitable for high speed operation?(6 marks) 5 (b) A multi-meter does not measure the 'true RMS value' of a voltage signal'. Justify. How can the true RMS value of a voltage signal be measured using analog multipliers?(10 marks) 6 (a) Design a moduo-10 counter with the counting sequence 5,6?.., 14,5,6?.,14 using MSI 74X163(10 marks) 6 (b) Draw the block diagram of internal architecture of XC 9500 family CPLD and explain the working of each block(10 marks) 7 (a) Write VHDL code for a four bit up counter(6 marks) 7 (b) Design a Moore machine for overlap sequence detector for the starting 1110. the output must be 1 when the input matches this string.
(i) Draw the state diagram
(ii) Write the transmission and output tables.
(iii) Draw the logic diagram
(14 marks)


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