Fundamentals of HDL - Jun 2013

Electronics & Communication (Semester 4)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks. 1 (a) Describe VHDL scalar data types with an example.(8 marks) 1 (b) Explain shift and rotate operators in HDL with an example.(8 marks) 1 (c) Write a note on simulation and synthesis.(4 marks) 2 (a) Explain the execution of signal assignment statements in HDL.(5 marks) 2 (b) Briefly discuss:
i) Constant declaration and assignment statement
ii) Signal declaration and assignment statement(6 marks) 2 (c) Write VHDL/Verilog code for 2×2 bit combinational array multiplier.(9 marks) 3 (a) Write VHDL code for 3 bit binary counter using CASE statement.(6 marks) 3 (b) Explain verilog cases. Write verilog description of priority encoder using casex statement.(6 marks) 3 (c) With syntax, explain the sequential statements in HDL:
i) IF statement
ii) IF as ELSE-IF
iii) For loop(8 marks) 4 (a) Write structural description of an VHDL SR latch using NOR gates.(8 marks) 4 (b) Write the facts of structural description.(4 marks) 4 (c) Write verilog code for N bit magnitude comparator using generate statement.(8 marks) 5 (a) Write VHDL code to convert unsigned binary vector to integer conversion using procedure.(8 marks) 5 (b) Explain the syntax of function in verilog with an example.(4 marks) 5 (c) Write VHDL code for reading a string of character from file and store in an array Ex: COLLEGE.(8 marks) 6 (a) Write VHDL code for 16×8 SRAM using mixed type description.(12 marks) 6 (b) Write verilog code for ALU using mixed type description.(8 marks) 7 (a) Write mixed language description of Master Slave D flip flop by invoking VHDL entity from verilog module.(10 marks) 7 (b) Explain the process of invoking a verilog module from VHDL module.(10 marks) 8 (a) With an example, explain mapping the function statement in HDL.(6 marks) 8 (b) Discuss some important facts related to synthesis basics.(6 marks) 8 (c) With an example, explain mapping if, if-else, case statement in HDL. Show the synthesized logic symbol and gate level diagram.(8 marks)