written 7.3 years ago by
teamques10
★ 64k
|
• modified 2.2 years ago |
Mumbai University > Electronics Engineering > Sem 3 > Digital circuits and design
Marks: 10M
Year: Dec 2015
|
written 7.3 years ago by
teamques10
★ 64k
|
| Asynchronous | Synchronous |
|---|---|
| 1.Clock pulse is given to first f/f and not simultaneously to all. | 1. Clock pulse is given to all flip-flops simultaneously. |
| 2. The o/p of preceding f/f (after 1st f/f) are given as i/p to clock pulse. | 2. The flip-flop connections are dependent on k-map equations- no present connections are done. |
| 3. Propagation delay is high so max frequency is low. | 3. Propagation delay is low so max frequency is high. |
| 4. Circuit is simple. | 4.Circuit becomes complex as states increases. |
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