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**Implement following function using 8:1 MUX and logic gates.**

written 7.3 years ago by

modified 2.2 years ago by

pedsangini276 • 4.7k

Mumbai University > Electronics Engineering > Sem 3 > Digital Circuits and Design

Marks: 10M

Year: May 2016

P (A, B, C, D) = ∑m (1, 2, 6, 7, 8, 10, 13, 14)

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Inputs	D0	D1	D2	D3	D4	D5	D6	D7
A’	0	1	2	3	4	5	6	7
A	8	9	10	11	12	13	14	15
Input to Mux	A	A’	1	0	0	A	1	A’