Question: Design a Mealy sequence detector to detect ...0101...using D-flip flop and logic gates

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State diagram will be,

States are as follows,

a=00, b=01, c=10, d=11

State table :-

Present | Next | State | Output | Output |
---|---|---|---|---|

State |
X=0 | X=1 | X=0 | X=1 |

a | b | a | 0 | 0 |

b | b | c | 0 | 0 |

c | d | a | 0 | 0 |

d | b | c | 0 | 1 |

To design a circuit:-

Input | Present | State | Next | State | F/F | I/P | O/P |
---|---|---|---|---|---|---|---|

X |
B |
A |
B |
A |
$D_{B}$ |
$D_{A}$ |
Y |

0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |

0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |

0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |

0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 |

1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |

1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |

**Input equation for $D_{B}$** :-

**Input equation for $D_{A}$ :-**

**Output equation:-**

**Circuit Diagram :-**

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