8051 contains to 16-bit timers

• T0 (timer 0)
• T1 (timer 1)

Two different types of timer

• Interval timer
• Counter

Maximum value is 65536

Initial state can be set by user

Timers / customers can be operated by user with special function registers T0 and T1 share two SFR’s: T MOD and T CON

Each timer has also two registers dedicated to itself TH0/TL0 and TH1/TL1

TMODC timer mode register is a non bit addressable 8 bit register

• Lower 4 bit are for timer 0
• Upper 4 bit are for timer 1
• GATE bit is used for choice of internal or external control
• GATE = 0 is for internal control start and stop are controlled by software
• GATE = 1 is for external control start and stop are controlled by software and external source
• $\frac{C}{\overline{T}}$ bit decides about timer type interval timer or counter
• Mo and M1 bits are used to set timer mode (same for timer 0 and timer 1)

TCON is a bit addressable 8-bit register where 4 upper bits are responsible for timers/counters

TR0 and TR1 are set by user to turn on (or turn off) timer 0 or timer 1

TR = 0 – turn OFF

TR = 1 – turn ON

TF0 and TF1 are timer flags informing about overflow (then TF=1 and interrupt could be activate if its set should be cleaned)

TH0 and TL0 are upper and lower register of timer 0

TH1 and TL1 are upper and lower register of timer 1

They help to set initial value of timer/counter

TF1: Timer 1 overflows flag set by hardware on timer counter overflow cleared by hardware

TR1: Timer 1 run control bit set/cleared by software to turn timer/counter on/off

TF0: Timer 0 overflow flag set by hardware on timer/counter overflow

TR0: Timer 0 run control bit set/cleared by software to turn timer/counter on/off

IE1: interrupt 1 edge flag set by hardware when external interrupt edge detected cleaned when interrupt processed.

IT1: interrupt 1 type control bit set/cleared by software to specify falling edge flow level triggered external interrupt.

IE0: interrupt 0 edge flag set by hardware when external interrupt edge detected cleaned when interrupt processed.

IT0: interrupt 0 type control bit set/cleared by software to specify falling edge low level triggered external interrupt.