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Computer Organization : Question Paper Dec 2013 - Electronics & Telecomm (Semester 3) | Visveswaraya Technological University (VTU)

Computer Organization - Dec 2013

Electronics & Communication (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
1 (a) With a general block diagram, explain the functions of each of the processor registers.(8 marks) 1 (b) Highlighting important technological features and advances, explain the evolution of computer over different generations.(8 marks) 1 (c) With suitable example, explain how performance is measured using SPEC rating and give its significance.(4 marks) 2 (a) Convert the following pair of decimal numbers into 5 bit singed 2's complement binary numbers and perform operations indicated. Also state if overflow occurs.
i) -10 and -13 (addition)
ii) -14 and 11 (subtraction)
iii) -3 and -8 (addition)
iv) -10 and -13 (subtraction)
(8 marks)
2 (b) Given the following instruction, rewrite using only direct, indirect and immediate addressing modes to achieve the same effect: move 123 (R1, R2), (R3, R4).(5 marks) 2 (c) What is a stack frame? Explain its use in subroutines.(7 marks) 3 (a) What is an interrupt? Explain its concepts and the hardware used to realize it.(6 marks) 3 (b) What is the necessary of DMA? Explain the two modes in which DMA interface operates to transfer data.(6 marks) 3 (c) Explain the bus arbitration approaches with the help of neat sketches.(8 marks) 4 (a) Explain the combined input/output interface circuit, with help of a neat logic block diagram.(10 marks) 4 (b) With respect to USB, discuss the USB architecture, addressing and protocol adopted.(10 marks) 5 (a) With a block diagram, explain the organization of 8M×32 memory using 512 K×8 memory chips.(10 marks) 5 (b) Explain the working of a dynamic memory cell.(5 marks) 5 (c) What is memory interleaving? Explain.(4 marks) 5 (d) Calculate the average access time experienced by a processor if cache hit rate is 0.88. miss penalty is 0.015 milliseconds and cache access time is 10 micros seconds.(4 marks) 6 (a) Explain how virtual machine address translation based on fixed-length pages is organized and achieved.(8 marks) 6 (b) Explain the design of a 4-bit carry - look-ahead adder.(8 marks) 6 (c) Write a note on optical technology used in CD systems.(4 marks) 7 (a) Draw the circuit diagram for binary division. Explain the non-restoring division algorithm with suitable example.(10 marks) 7 (b) Explain the IEEE standard for floating point number representation.(10 marks) 8 (a) Mention and explain the control sequences for execution of an unconditional branch instruction.(10 marks) 8 (b) With a block diagram, explain the basic organization of a micro-programmed control unit.(10 marks)

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