Computer Organization & Architecture - May 2014
Computer Engg (Semester 3)
TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
Answer any one question from Q1 and Q2
1 (a) Using Booth's algorithm multiply the following Multiplicand = 7, Multiplier = 3(6 marks)
1 (b) Explain IEEE 488 format for single precision and double precision floating point numbers with example.(6 marks)
2 (a) Explain the various speeds up techniques of processor.(4 marks)
2 (b) Explain following addressing modes of 8086 with suitable examples
i) Index Addressing
ii) Register Indirect
iii) Auto Increment
iv) Relative Addressing(8 marks)
Answer any one question from Q3 and Q4
3 (a) Draw flowchart for Non restoring Division algorithm.(6 marks) 3 (b) Write control sequence for execution of the instruction Add (R3), R1(6 marks) 4 (a) Explain the Key components of the front end of the Intel Nehalem architecture.(6 marks) 4 (b) What are the different design methods for Hardwired control units? Explain any one.(6 marks)
Answer any one question from Q5 and Q6
5 (a) Explain cache mapping techniques with example.(6 marks)
5 (b) Explain Intel Nehalem memory organization with diagram.(7 marks)
6 Write short Notes (Any Three)
USB Packet Format
PCI Bus(13 marks)
Answer any one question from Q7 and Q8
7 (a) Draw and explain block diagram of Itanium processor.(6 marks)
7 (b) Write short note on
i7 Mobile Version
Instruction format of IA-64 architecture.(7 marks) 8 (a) Explain the architecture of CBE processor with the help of block diagram.(6 marks) 8 (b) Write short note on
Sun UltraSparc T1
NVIDIA GPU(7 marks)