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Computer Organization - Dec 2014
Computer Engg (Semester 4)
TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
Answer any one question from Q1 and Q2
1 (a) Draw and explain Von Neumann architecture.(6 marks)
1 (b) Explain basic SOC (System on Chip) processor architecture.(6 marks)
2 (a) Describe the features of RISC and CICS processors.(6 marks)
2 (b) Multiply the following numbers using Booth's algorithm:
Multiplicand = +13
Multiplier = ?6 (Show steps in detail).(6 marks)
Answer any one question from Q3 and Q4
3 (a) Explain hardware organization and execution of 4 stage instruction Pipeline.(6 marks) 3 (b) State Microinstructions for Add (Rscr)+, Rdst.(6 marks) 4 (a) Explain with example the steps involved in floating point addition and multiplication.(6 marks) 4 (b) Compare hardwired and micro programmed control unit.(6 marks)
Answer any one question from Q5 and Q6
5 (a) Compare memory mapped I/O with I/O mapped I/O.(6 marks) 5 (b) Explain how data transfer takes place by USB.(7 marks) 6 (a) Compare NUMA and UMA multiprocessors.(6 marks) 6 (b) Explain how data transfer takes place by SCSI Bus.(7 marks)
Answer any one question from Q7 and Q8
7 (a) Draw the block diagram of AMD multicore Opteron.(6 marks) 7 (b) Draw NVDIA GPU architecture.(7 marks) 8 Explain with diagram Intel IA-64 architecture.(13 marks)