Question Paper: Digital Electronics : Question Paper Dec 2016 - Computer Engineering (Semester 3) | Gujarat Technological University (GTU)
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Digital Electronics - Dec 2016

Computer Engineering (Semester 3)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS
(1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.
1(a) (56)16=(?)10(1 marks) 1(b) (32)10=(?)2(1 marks) 1(c) Bubbled OR gate is also called________.(1 marks) 1(d) Define: Fan in(1 marks) 1(e) Define: Noise Margin(1 marks) 1(f) Design a NOT gate using a two input EX-OR gate.(1 marks) 1(g) Which logic family is the fastest logic family?(1 marks) 1(h) Why ROMs are called nonvolatile memory?(1 marks) 1(i) What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations.
b) The J represents "jump", which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
c) The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
d) All of the other letters of the alphabet are already in use.
(1 marks)
1(j) How many inputs are required for 1-of-16 decoder?
a) 2 b) 4 c) 8 d) 12
(1 marks)
1(k) State the distributive property of Boolean algebra.(1 marks) 1(l) Which logic family consumes the less power?(1 marks) 1(m) Define: Negative Logic(1 marks) 1(n) How many flip fops are required to count the sequence from 0 to 63?(1 marks) 2(a) Why NAND gate is known as universal gate?(3 marks) 2(b) Find the 10's complement of the following: 1) (935)11 2) (6106)10(4 marks)


Solve any one question.Q2(c) &Q2(d)

2(c) Design 3-bit parity generator circuit using even parity bit.(7 marks) 2(d) Using D as the VEM, reduce
Y=A' B' C' D'+ A 'B'CD'+ AB'C'D+AB'C'D+AB'CD'+AB'CD.
(7 marks)


solve any one question Q.3(a,b,c) &Q4(a,b,c)

3(a) Obtain the truth table of the function: F=xy+xy'+y'Z.(3 marks) 3(b) Explain RS flip flop in detail.(4 marks) 3(c) Explain full adder and design a full adder circuit using 3 to 8 decoder and two OR gates.(7 marks) 4(a) Design one bit magnitude comparator.(3 marks) 4(b) Implement the given function using multiplexer. F (A, B, C) =∑(1,3,5,6)(4 marks) 4(c) Design BCD to Excess-3 code convertor circuit.(7 marks)


solve any one question Q.5(a,b,c) &Q6(a,b,c)

5(a) Show that ( A+C) (A+D) (B+C) (B+D) = AB+CD(3 marks) 5(b) Explain Moore machine.(4 marks) 5(c) Design Modulo-8 counter using T flip flop.(7 marks) 6(a) Explain edge triggering and level triggering.(3 marks) 6(b) Explain 4 bit serial in serial out shift register.(4 marks) 6(c) Design 3-bit synchronous up counter using T flip flop.(7 marks)


solve any one question Q.7(a,b,c) &Q8(a,b,c)

7(a) Give classification of logic families. Also list the characteristics of digital IC.(3 marks) 7(b) Explain Half Adder circuit with neat diagram.(4 marks) 7(c) Write short note on Read Only Memory (ROM).(7 marks) 8(a) What is race around condition JK flip flop.(3 marks) 8(b) How does a counter works as frequency divider? Explain with suitable example.(4 marks) 8(c) A combinational logic circuit is defined by the functions: F1=∑(3, 5, 6, 7) and F2=∑(0, 2, 4, 7). Implement the circuit with a PLA having three inputs, four product terms and two outputs.(7 marks)

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