Single ended signaling & differential ended signalling

Subject: CMOS VLSI Design

Topic: Differential Amplifiers

Difficulty: Medium

cvd • 713  views

i) An important advantage of differential signalling over single ended signalling is higher immunity to environmental noise.

ii) Consider fig:(a)
Clock line- carries a large clock signal.
Signal line- carries small sensitive signal.
Due to capacitive coupling between two lines, transitions on clock line may corrupt signals on signal line.

iii) This effect of coupling can be reduced by differential signalling.

enter image description here

iv) Consider fig:(b)
Signal: - transmitted on 2 different lines.
- same magnitude & opposite phase.
Clock line: - placed between 2 signal lines.

v) Since, signal on both the lines is same and out of phase, effect of clock line on signal line will be zero, If we take difference of two signal lines at the end.

enter image description here

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