Explain PLL Topology

Subject: CMOS VLSI Design

Topic: Mixed Signal Circuits

Difficulty: Medium

cvd • 679  views

i) A PLL consists of a PD ( Phase detector) and a VCO (Voltage controlled Oscillator) in a feedback loop.

ii) PD compares phase of $V_{out}$ and $V_{in}$ generating an error that varies the VCO frequency untill the phases are aligned. i.e loop is locked.

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iii) This topology, however must be modified because, $\omega /f$ at output stage PD($V_{PD}$) consists of a dc component (desirable) and high frequency components (undesirable).

iv) The control Voltage of oscillator must remain quiet in the steady state i.e PD output must be filtered.
Therefore, interpose a LPF between PD and VCO.

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