VLSI Design - December 2016

MU Electronics and Telecom Engineering (Semester 6)

Total marks: --
Total time: -- INSTRUCTIONS
(1) Assume appropriate data and state your reasons
(2) Marks are given to the right of every question
(3) Draw neat diagrams wherever necessary

Solve any four questionQ.1(a,b,c,d,e)

1(a) Explain any two properties of autocorrelation function. 5 marks

1(b) How to distribute a clock properly in VLSI chip? 5 marks

1(c) Draw layout for minimum size 6T SRAM cell. 5 marks

1(d) Explain the issues associated with pass transistor logic with suitable example. 5 marks

1(e) Explain constant voltage scaling? 5 marks

2(a) Explain the fabrication process flow for NMOS with proper device cross section and layout. 5 marks

2(b) Explain pseudo NMOS logic with suitable example. 5 marks

2(c) Show realization of MOSFET based one Bit Shift Register. 5 marks

3(a) Design the circuit and draw layout for the function Y=(D+E+A)(B+C) using CMOS logic. Also find equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming that (W/L)_p=30 for all (W/L) _n=10 for all NMOS transistors. 5 marks

3(b) What are the problems of Domino logic? Also suggest remedy for these problems. 5 marks

4(a) With neat diagrams explain the principle of working of NOR flash. 5 marks

4(b) Draw and explain Barrel shifter. 5 marks

4(c) Draw schematic and layout for 4:2 decoder. 5 marks

5(a) Explain ripple carry adder in detail. 5 marks

5(b) Explain how to ensure faithful write operation in case of 6 T SRAM Cell. 5 marks

5(c) Compare LEVEL 1 and LEVEL 2 MOSFET model. 5 marks

6(a) With suitable diagrams explain on chip clock generation circuit. 5 marks

6(b) Explain a typical power distribution scheme followed in VLSI chip. 5 marks

6(c) Describe the dynamic power dissipation in CMOS. 5 marks

6(d) Expalin Latch-up in CMOS. 5 marks