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Design VHLD Program EX-OR gate?
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written 5.5 years ago by |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity xor1 is
Port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor1;
architecture xor11 of xor1 is
begin
y<= a xor b;
end xor11;