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What are advantages of VHDL. Write VHDL program for full adder.
1 Answer
written 5.6 years ago by |
Advantages of VHDL :
i. Executable specification
ii. Validate spec in system context (Subcontract)
iii. Functionality separated from implementation
iv. Simulate early and fast (Manage complexity)
v. Explore design alternatives
vi. Get feedback (Produce better designs)
vii. Automatic synthesis and test generation (ATPG for ASICs)
viii. Increase productivity (Shorten time-to-market)
ix. Technology and tool independence (though FPGA features may be unexploited)
x. Portable design data (Protect investment)
VHDL Code for a Full Adder
Library ieee;
use ieee.std_logic_1164.all;
entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;
architecture data of full_adder is
begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;
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