Working of N-channel JFET

• Following fig. (a) shows biasing condition for working of N-channel JFET

• In above figure battery source voltage VGG is applied between gate to source to make P-N junction reverse bias.

• A positive voltage is applied between drain and source terminal.

• We can consider following condition to observe working of N-channel JFET

A) when VGS =0v

• Following fig(b) shows the N-channel JFET when no bias is applied between gate and source

• When VGS=0v and external voltage VDSis applied between drain and source, the electrons flows from source to drain through the narrow channel.

• This constitute the drain current (ID) and its conventional direction is indicated from drain to source

B) When VGS, increased

• Following fig (c) shows the biasing of N channel JFET when VGS has some finite value

• VGS is applied to make junction between gate to source reverse.

• When this reverse bias voltage VGS is increased the depletion region becomes more wide. This reduces the effective width of the channel and therefore controls the flow of current through channel.

• When gate to source voltage increased further a stage is reached at which two depletion region touch each other as shown in fig (d).

• At this stage the channel is completely blocked or pinch off and drain current reduced to zero

• The gate to source voltage at which the drain current is zero is called as pinch off voltage (VP).

Symbol

• The following fig (e) shows schematic symbol for N-channel JFET

• In symbol vertical line represents N channel

• Characteristics of N channel JFET