-------- Up Counter --------
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
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ENTITY Up Counter IS
GENERIC (bits: 3); 
PORT (a: IN BIT_VECTOR(bits-1 DOWNTO 0):
clk: IN BIT;
count: OUT BIT_VECTOR(bits-1 DOWNTO 0));
END Up Counter;
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ARCHITECTURE behavioral OF Up Counter IS
BEGIN
count <= 3'b000;
a <= 3'b001;
PROCESS (clk)
BEGIN
count <= count + a;
END PROCESS;
END behavioral;