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IC Technology - May 16
Electronics Engineering (Semester 7)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Q1) Solve any four of the following:
1(a)
Explain Interstitial and substitutional diffusion process.
(5 marks)
2511
1(b)
Explain Electronics package reliability.
(5 marks)
2842
1(c)
Explain the concept of clean rooms.
(5 marks)
2236
1(d)
Explain Nuclear and electronic stopping mechanisms in lon implantation with neat
diagrams.
(5 marks)
2805
1(e)
Give the steps in a standard RCA cycle during wafer cleaning.
(5 marks)
2237
2(a)
What is lon Implantation? Explain the process with a neat diagram.
(10 marks)
2804
2(b)
Describe optical lithography with the help of a neat diagram.
(10 marks)
2818
3(a)
Explain the fabrication process step along with vertical cross-sectional views for CMOS Inverter using twin tub process.
(10 marks)
2830
3(b)
With neat diagram explain the Float Zone technique of crystal growth.
(10 marks)
2245
4(a)
What is the significance of Design rules? Draw layout for the CMOS inverter using lambda (λ) based design rules.
(10 marks)
2831
2834
4(b)
Discuss Etching methods for photoresists removal.
(10 marks)
2810
5(a)
Explain SOI fabrication using bonded SOI and smart cut method.
(5 marks)
2850
5(b)
State advantages of BICMOS over CMOS.
(5 marks)
2865
5(c)
Describe with the help of a neat diagram Hayness-Schokley experiment for measurement of Drift Mobility of n-type semiconductor.
(10 marks)
2839
Q6) Write short notes on any four of the following:
6(a)
MODFET and optoelectronics devices
(5 marks)
2861
2862
6(b)
Nanowire transistor
(5 marks)
2870
6(c)
Molecular Beam epitaxy
(5 marks)
2500
6(d)
Second order effects in bipolar transistor
(5 marks)
2863
6(e)
VLSI Technology Trends affecting Testing
(5 marks)
2843
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