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Draw neat block diag of delta modulator Transmitter and Receiver and explain it working.

Subject: Computer Engineering

Topic: Electronic Circuits and Communication Fundamentals

Difficulty: Medium / High

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Delta Modulator Transmitter:

Operation: X(t) – i/p signal to comparator

X’(t) – quantized version of x(t)

In comparator,↑ high if x(t) > x’(t) and goes low ↓ if x(t) < x’(t). Thus the comparator o/p os either 1 or 0.

The sample and hold circuit will hold this level (0/1) for the entire clock cycle period.

The o/p of sample and hold is transmitted as o/p of DM system. Also, one bit per clock cycle is sent. Thus bit rate and b.w is reduced.

The sig is used to decide the mode of operation of an up/down counter, the counter o/p increments by 1 if $S_o (t)=1$ and it decrements by 1 if $S_o (t)=0,$ at the falling edge of each clock pulse.

1. Low signaling rate and low transmission channel b.w because in delta modulation, only one bit is transmitted per sample.
2. The d.m transmitter and receiver are not complicated.