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Computer Organization And Architecture Question Paper - Dec 17 - Computer Engineering (Semester 4) - Mumbai University (MU)
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Computer Organization And Architecture - Dec 17

Computer Engineering (Semester 4)

Total marks: 80
Total time: 3 Hours

Instructions:
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume suitable data if required (4) Draw neat diagrams wherever necessary.

Q1 Solve any Four

1.a List different memory organization characteristics.
(5 marks) 5797

1.b What is IO buffering?
(5 marks) 12547

1.c In Floating point representation how to identify sign of exponent?
(5 marks) 12555

1.d What is virtual memory?
(5 marks) 5791

1.e What is TLB?
(5 marks) 12550

2.A.1 Draw the flow chart for Booth's Algorithm for two's complement multiplication.
(4 marks) 5778

2.A.2 Using Booth's algorithm Multiply 14 times - 5.
(6 marks) 00

2.B Describe hard-wire control unit and specify its advantages.
(10 marks) 5785

3.A Compare interrupt driven I/o and DMA.
(10 marks) 5809

3.B Calculate the hit and miss using various page replacement policies LRU, OPT, FIFO for following sequence (page frame size 3) 4,7,3,0,1,7,3,8,5,4,5,3,4,7,534 state which one is best for above example?
(10 marks) 12556

4.A Explain set associative and associative cache mapping techniques.
(10 marks) 5799

4.B Explain Flynn's classification.
(10 marks) 5815

5.A Explain six stage instruction pipeline with suitable diagram.
(10 marks) 5814

5.B.1 Differentiate between I. RISC and CISC II.
(5 marks) 12553

5.B.2 Differentiate between SRAM and DRAM.
(4 marks) 12557

6.A Explain different pipe lining hazards
(10 marks) 12554

6.B Explain in brief cache coherency problem.
(10 marks) 5793

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