Module; Data Mover

Memory: A[2]; B[2]; C[2].
Inputs     :X[2].
Outputs  : Z[2].
1.  A<-X.
2.  C<-A.
3.  B<-C[0], C[1].
4.  C<-A V B.
5.  Z = C.end sequence.

Subject : Digital System Design (MU - ELEX Sem 4)

Lesson : ASM chart and RTL

Difficulty : Medium