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VLSI Design Question Paper - Dec 17 - Electronics And Telecomm (Semester 6) - Mumbai University (MU)
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VLSI Design - Dec 17
Electronics And Telecomm (Semester 6)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1
a)
Explain the Need & Effect of scaling
(5 marks)
00
b)
Find resistance $R_n$ for nMOS if electron mobility $\mu_n$ = 560$cm^2$/V-sec,
(5 marks)
00
$t_{0x}$ = 10nm, and $V_G$ = 3.3 Volts $V_{THn}$ = 0.7 Volts if W= 10$\mu$m L=0.5$\mu$m
c)
Expalin Latch-up problem in CMOS and how it can be avoided
(5 marks)
00
d)
Draw the circuit and explain the working for bidirectional pad
(5 marks)
00
2
a)
Design CMOS inverter such that the switching threshold is $V_{th}$ = 1.2 V, with the follwoing device parametres:
(10 marks)
00
NMOS: $V_{T0,\pi}$ = 0.6V $\mu_nC_{ox}$ = 60 $\mu$A/$V^2$
PMOS: $V_{T0,\pi}$ = -0.8V $\mu_pC_{ox}$ = 20 $\mu$A/$V^2$
Assume $V_{DD}$ = 2.4V and $\pi$ = 0
b)
Derive expression for current in saturation region from that of the linear region current equation also explain the effect of substracte potential (Body effect) on current and also discuss the effect on overall performance of the device.
(10 marks)
00
3
a)
Explain the effect of scaling on interconnects and comment on performance of VLSI circuit
(10 marks)
00
b)
Draw the schematic of carry look-ahead adder Explain how speed can be improved?
(10 marks)
00
4
a)
$F= \frac{}{a.b + c.d.e}$
(10 marks)
00
Consider the logical function as given above
- Design the CMOS logic gate that provides the function.
- Is it possible to find an Euler graph for the circuit? If so, construct the graph and also it to perform stick level layout. if not find a Layout strategy for the GATE.
b)
For the function Z = $\frac{}{(A+B)(E+F)(H+I)}$
(10 marks)
00
- Domino CMOS circuit
- Draw an equivalent circuit for domino circuit by using equivalent transistor sizes with W/L = 30/2 (both for NMOS and PMOS)
5
a)
Explain the Latch - up problem in CMOS with neat diagram also give the different methods to overcome the latch-up.
(5 marks)
00
b)
Compare various loads used in Inverter circuit. Draw proper diagram and compare different parameters which characterize each type of inverters.
(10 marks)
00
c)
Draw the Schematic of 6-transistors SRAM cell also the draw layout for the same.
(5 marks)
00
6
a)
Explain the clock generation and different types of clocking schemes for VLSI circuit. Explain various issues of clock distribution? Explain how they are addressed?
(10 marks)
00
b)
How the cross-talk in multilayer systerm is modeled?
(5 marks)
00
c)
Explain charge sharing problem and give the solution.
(5 marks)
00
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