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VLSI Design Question Paper - May 18 - Electronics And Telecomm (Semester 6) - Mumbai University (MU)
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VLSI Design - May 18
Electronics And Telecomm (Semester 6)
Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
Q1 Attempt any four form the following:
a)
Calculate the voltage at the output node $V_o$ if $V_{DD}$ = 5V and $V_{th}$ = 1.5V $V_{DD}$
(5 marks)
00
b)
Implement 2:1 multiplexer circuit using pass transistor logic and state its drawback. Draw the circuit using CMOS transmission gates.
(5 marks)
00
c)
State the conditions required for the symmetric static CMOS inverter.
(5 marks)
00
d)
Compare ion implantation with diffusion stating its advantages and disadvantages.
(5 marks)
00
e)
In 2-input CMOS NAND gate all PMOS transistors have (W/L)p=20 and all NMOS transistors have (W/L)n=10. Draw its equipment CMOS inverter for simultaneous switching of all inputs and find size of PMOS and NMOS transistor in the equipment inverter circuit.
(5 marks)
00
Q2)
a)
A CMOS inverter has following parameters.
(10 marks)
00
$V_{DD}$ = 3.3 V $V_{t0.n}$ = 0.6V $V_{t0.p}$ = -0.7V
$K_n$ = 200$\mu A/V^2$ $K_p$ = 80 $\mu A/V^2$
Calculate the noise margin of the circuit. Is the inverter symmetric?
b)
Implement Y=$\frac{}{A(B+C) + DE}$
(10 marks)
00
i) static CMOS logic
ii) Dynamic logic
iii) Depletion load logic
iv) Pseudo NMOS logic
Q3)
a)
Explain in detail the fabrication sequence of PMOS transistor with cross sectional view of each step.
(10 marks)
00
b)
Draw schematic and layout diagram of six transistor SRAM cell and explain Read and write operations.
(10 marks)
00
Q4)
a)
Compare constant field scaling with constant voltage scaling and state advantages and limitations in both the methods. Show the effect of scaling on power density and current density.
(10 marks)
00
b)
Design a 3-bit genarator block of carry look ahead adder using multiple output domino logic (MODL) style. Explain how it achieves better speed compared to ripple carry adder.
(10 marks)
00
Q5)
a)
Draw layout diagram of two input CMOS NAND gate using lambda design Rules with $(L/W)_p$ = 1/2 and $(L/W)_n$ = 2/1. (Indicate scale in terms of lambda on layout).
(10 marks)
00
b)
Draw transistor level CMOS negative edge triggered master salve D flip flop.
(5 marks)
00
c)
What are the limitations of single phase clock? Explain with neat diagram two phase clock system.
(5 marks)
00
Q6) Note short notes on any four
i)
ESD protection circuit
(5 marks)
00
ii)
4x4 Barrel shifter
(5 marks)
00
iii)
MOSFET Capacitances
(5 marks)
00
iv)
Design rules and their necessity
(5 marks)
00
v)
Clock skew and clock jitter
(5 marks)
00
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