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CMOS VLSI Design Question Paper - Dec 17 - Electronics Engineering (Semester 8) - Mumbai University (MU)

## CMOS VLSI Design - Dec 17

### Electronics Engineering (Semester 8)

Total marks: 80

Total time: 3 Hours
INSTRUCTIONS

(1) Question 1 is compulsory.

(2) Attempt any **three** from the remaining questions.

(3) Draw neat diagrams wherever necessary.

**1.a.**Analyze following circuit to get voltage gain equation if M2 is twice wide as that of M1 and Vin1=Vin2

**1.b**Explain importance of Miller Theorem

**1.c**Explain input output characteristics of phase detector (PD) circuit

**1.d**Draw and explain AMS design flow

**2.a**Derive expression for Voltage gain Av and output resistance Ro of Source follower stage.

**2.b**Explain in detail how to generate temperature independent references.

**3.a**Explain qualitative analysis of differential pair.

**3.b**Explain concept of switched capacitor circuits and hence explain switched capacitor amplifiers in detail.

**4.a**Explain common mode response of differential pair with necessary derivations.

**4.b**Explain White & Flicker noise in MOSFET. Derive equation for output and input referred noise voltage of CS stage.

**5**Design two stage Operational Transconductance Amplifier(OTA) to meet following specifications-with a phase margin of 60, A$_V$>4000v/v ,V$_{dd}$=2.5V, V$_{ss}$= -2.5v, GBW=6MHz, CL=10pf, SR>10v/$\mu$sec, Vout range= +/- 2V, ICMR=-1.125V to 2V, Pdiss<=2.5mw Use, K$_N$=110$\mu A/V^2$, K$_P$=50$\mu A/V^2$, V$_{TN}$=$\mid$V$_{TP} \mid$=0.7V, $\lambda _N$=0.04V$^{-1}$, and $\lambda _P$=0.05V$^{-1}$ , Cox=2.47fF/$\mu m^2$, Verify that the designed circuit meets required Voltage Gain and Power Dissipation specifications.

**6.a**Give comparison between Full-custom and Semi-custom design.

**6.b**Compare various opamp topologies

**6.c**Explain in detail charge pump PLL

**6.d**Write a short note on Gilbert Cell

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