Question Paper: Microprocessors and Applications Question Paper - May 18 - Electronics Engineering (Semester 4) - Mumbai University (MU)
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Microprocessors and Applications - May 18

Electronics Engineering (Semester 4)

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

1.Answer the following questions:

1.a. Explain the feature of pipelining and queue in 8086 architecture.
(4 marks) 9042

1.b. Explain the significance of TEST, RESET and MN/MX signals in 8086 processor ( * indicates bar).
(4 marks) 9052

1.c. List the steps taken by 8086 processor in response to receiving an interrupt.
(4 marks) 9058

1.d. In 8086 bus cycle, explain the significance of ALE signal.
(4 marks) 9054

1.e. Explain the flag register for 8086 processor.
(4 marks) 9053

2.a. List and explain with examples addressing modes of 8086 processor.
(10 marks) 12029

2.b. Explain with the help of neat diagram and interfacing of 8086-8087 closely coupled configuration system.
(10 marks) 9061

3.a. a) with the help of memory map interface the following to an 8086 based system operating in minimum mode: (14) a) 32k bytes of EPROM memory using 8k byte devices. b) 32k bytes of RAM memory using 8k byte devices. c) One 16 – bit input and output port.
(14 marks) 9060

3.b. Explain the following 8086 instructions (ANY THREE) a) CMPSB b) DIV AX c) LOOPE again d) REP SCASB e) XLATB
(6 marks) 9056

4.a Write a detailed note on the interrupt structure of 8086 processor.
(10 marks) 9059

4.b. Explain the need of DMA and modes of DMA data transfer typically made use of by DMA controller IC – 8237.
(10 marks) 9064

5.a. Explain the Intel Pentium processor’s pipelining and superscalar architecture.
(10 marks) 9065

5.b. With the help of a neat flowchart/algorithm write a program in 8086 assembly to arrange a set of ten 8-bit numbers initialized in data segment in ascending order.
(10 marks) 9057

6. Write short notes on: [ANY TWO]

6.a. Programmable interrupt controller – 8259.
(10 marks) 9062

6.b. Intel Pentium processor – Branch prediction Logic
(10 marks) 9066

6.c. Programmable peripheral interface – 8255, need for and operation in Mode – 1.
(10 marks) 12030

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modified 5 months ago  • written 5 months ago by gravatar for Ankit Pandey Ankit Pandey70
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