Subject: Principles of Communication Engineering

Difficulty : Medium

Marks : 10

Delta modulation has two major drawbacks that are:

1. Slope overload distortion

   This distortion arises because of large dynamic range of input signal. To reduce this error, the step size must be increased when slope of signal x(t) is high. Since the step size of delta modulator remains fixed, its maximum or minimum slopes occur along straight lines. Therefore, this modulator is known as Linear Delta Modulator (LDM).

2. Granular noise

   Granular noise occurs when step size is too large compared to small variations in the input signal. This means that for very small variations in the input signal, the staircase signal is changed by large amount because of large step size. The error between the input and approximated signal is called granular noise. The solution to this problem is to make step size small. Adaptive Delta Modulation

   To overcome the quantization error due to slope overload distortion and granular noise, the step size (Δ) is made adaptive to variations in input signal x(t). Particularly in the step segment of the x(t) , the step size is increased. Also, if the input is varying slowly, the step size is reduced. Then this method is known as Adaptive Delta Modulation (ADM). The adaptive delta modulators can take continuous changes in the step size or discrete changes in the step size.

Adaptive Delta Modulation:

Step size is not constant.

Rather when the slope over load occurs the step size becomes progressive larger and ∴ x(+) will catch up with x(+) more rapidly.

The step size is adaptive as per level of i/p signal.

As shown, X (t) is the analog input signal & x' (t) is the quantized version of x(t). Both these signal are applied to comparator. Comparator output is goes high if $x(t) \ge x'(t)$ & it goes low if $x(t) \le x'(t)$. Thus the comparator output is either 1 or 0.Sample & hold circuit will hold this level for entire clock cycle. In response to kth clock pulse trailing edge, a processor generates a step which is equal in magnitude to the step generated in response to the previous i.e. (k-1)th clock edge. If the direction of both the step is same then the processor will increase the magnitude of present step by delta. If the direction is opposite then the processor will decrease the magnitude of present step by delta.

If compared with linear delta modulator, then you will find that except for the counter being replaced by digital processor, removing blocks are identical.

And $S_o (t)=-1 $ if $x(t) \le x’(t)$ just before kth clock edge.

Then step size at sampling instant k is :-

$S(k) = [δ(k-1)] S_o (k)+δ S_o (k-1)$

ADM Receiver:

ADM signal 1st converted into a DM signal with help of step size control logic and then applied to DM receiver.

AT o/p of low pass filter we get original signal.