VLSI Design Question Paper - Dec 17 - Electronics Engineering (Semester 6)

57views

written 5.1 years ago by

VLSI Design - Dec 17

Electronics Engineering (Semester 6)

TAKEN FROM CREDIT BASED PATTERN

Total marks: 80
Total time: 3 Hours INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Q.1. Solve Any 4

1.a. Compare BJT & CMOS technology in VLSI design.

(5 marks) 8548

1.b. Implement the following function using Dynamic CMOS logic.

$Y =\overline{(A.B)+(C.D)}$

(5 marks) 8561

1.c. Implement half adder circuit using static CMOS.

(5 marks) 8593

1.d. Implement $4*4$ NAND based ROM array

(5 marks) 8582

1.e. Explain importance of low power design.

(5 marks) 8600

2.a. What are the different MOSFET Models?Give importance of MOSFET capacitance related to MOSFET's

(10 marks) 8554

2.b. Explain transfer characteristic for CMOS.Inverter Showing different regions.What is the effect of variation in W/L ratio?

(10 marks) 8557

3.a. Draw 6T SRAM Cell and explains it's read and write operation.

(10 marks) 8575

3.b. Explain Scheme for multiplication $110*100$

(10 marks) 8588

4.a. Explain various techniques of clock generation and clock distribution.

(10 marks) 8596

4.b. Implement 4:1 multiplexer using NMOS pass transistor logic.

(10 marks) 8567

5.a. Draw D Flip Flop using CMOS and explain the working.

(10 marks) 8562

5.b. Draw CLA (carry lookahead adder) carry chain using static CMOS logic.

(10 marks) 8589

Q.6. Write Short notes on

6.a. Interconnect Scaling

(5 marks) 8550

6.b. Latch UP in CMOS

(5 marks) 12268

6.c. Decoder in Memory Structure

(5 marks) 8576

6.d. ESD protection.

(5 marks) 8597

ADD COMMENT EDIT