VLSI Design Question Paper - May 18 - Electronics Engineering (Semester 6)

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VLSI Design - May 18

Electronics Engineering (Semester 6)

TAKEN FROM CREDIT BASED PATTERN

Total marks: 80
Total time: 3 Hours INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Q.1. Solve Any 4

1.a. What are different MOS capacitances? Explain in brief.

(5 marks) 8551

1.b. Implement the following function using Static CMOS logic.

$Y =\overline{(A.B)+(C.D)}$

(5 marks) 8573

1.c. What is low power design in VLSI circuit.

(5 marks) 8600

1.d. Define scaling.Explain significance of scaling in VLSI circuits.

(5 marks) 8552

1.e. Explain working of 1-T DRAM cell

(5 marks) 8579

2.a. Explain CMOS inverter characteristics mentioning all regions of operation.What is the effect of changing W/L ratio on it?Explain with example.

(10 marks) 8557

2.b. Implement 4:1 mux using pass transistor logic.Explain advantages of using transmission gate.

(10 marks) 8567

3.a. Derive equation of noise margin for CMOS inverter.

(10 marks) 8559

3.b. Explain working of 6-T SRAM cell.

(10 marks) 8575

4.a. Explain Clock generation networks and distribution networks used in VLSI circuits.

(10 marks) 8596

4.b. What is fast adder?Explain any one scheme for fast adder.

(10 marks) 8592

5.a. Explain pseudo NMOS logic and hence implement 2 I/P NAND gate.

(10 marks) 8568

5.b. Explain various ESD protection technique.

(10 marks) 8597

Q.6. Write Short note on

6.a. Barrel shifter.

(5 marks) 8591

6.b. NOR based ROM array

(5 marks) 8581

6.c. Interconnect scaling.

(5 marks) 8550

6.d. Level-1 and Level-2 MOS model.

(5 marks) 8553

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