0
877views
Digital System Design Question Paper - May 18 - Electronics And Telecomm (Semester 3) - Mumbai University (MU)
1 Answer
0
27views

Digital System Design - May 18

Electronics And Telecomm (Semester 3)

Total marks: 80
Total time: 3 Hours

INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

1.a. If $F(A,B,C)=\sum m(0,3,5,7)$ with its truth table and express F in SOP and POS form
(5 marks) 00

1.b. Compare TTL and CMOS Logic families
(5 marks) 00

1.c. Perform the following operation using 2's compliment

i. $(7)_{10}-(15)_{10}$

ii. $(50)_{10}-(2A)_{16}$

Comment on the results of (i) and (ii)

(5 marks) 00

1.d. Compare SRAM with DRAM
(5 marks) 00

2.a. Implement following Boolean function using 8:1 multiplexer

$F(A,B,C,D)=\bar AB \bar D+ACD+\bar BCD+ \bar A \bar CD$

(10 marks) 00

2.b. Design 3 bit Binary to Gray code Converter
(10 marks) 00

3.a. What are shift registers? How are they classified? Explain working of any one type of shift register.
(10 marks) 00

3.b. Write VHDL code for 3 bit up counter
(10 marks) 00

4.a. Explain Master Slave JK Flip flop
(5 marks) 00

4.b. Convert T flip flop to D flip flop
(5 marks) 00

4.c. Minimize the following expression using Quine McClusky Technique

$F(A,B,C,D)=\sum m(1,3,7,9,10,11,13,15)$

(10 marks) 00

5.a. State and prove DeMorgan's Theorem
(5 marks) 00

5.b. Convert $(532.125)_8$ into decimal, binary and hexadecimal.
(5 marks) 00

5.c. Explain Full Adder circuit using PLA having three inputs, 8 product terms and two outputs
(10 marks) 00

6.a. Prove that NAND and NOR gates are universal gates
(10 marks) 00

6.b. Draw and explain 3 bit asynchronous binary counter using positive edge triggered JK flip flop. Draw the waveforms
(10 marks) 00

Please log in to add an answer.