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Logic Design Question Paper - Dec 18 - Information Technology (Semester 3) - Mumbai University (MU)

## Logic Design - Dec 18

### Information Technology (Semester 3)

Total marks: 80

Total time: 3 Hours
INSTRUCTIONS

(1) Question 1 is compulsory.

(2) Attempt any **three** from the remaining questions.

(3) Draw neat diagrams wherever necessary.

**1.a.**What are the important features of differential amplifier, also states its types.

**1.b.**State De'sMorgon theorem & implement OR gate using NAND gate only.

**1.c.**ADD $(83)_{10}$ & $(34)_{10}$ in BCD.

**1.d.**Convert S-R flip flop to D flip-flop.

**1.e.**State advantages & disadvantages of multiplexer.

**1.f.**Explain VHDL format in brief.

**2.a.**Simplify the following using Quine-Mcclusky method.

$\mathrm{F}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum \mathrm{m}(0,3,4,11,15)+\mathrm{d}(1,2,5)$

**2.b.**Design & implement one digit BCD adder using IC 7483.

**3.a.**Design

**MOD-11**ripple counter using suitable flip-flop.

**3.b.**Convert the following decimal number into binary, octal & hexadecimal.

- $(555)_{10}$ 2. $(138)_{10}$ 3. $(79)_{10}$

**3.c.**Why transistor biasing is required, state factors required for it .

**4.a.**Draw truth table of full subtractor & realize using 3-8 decoder.

**4.b.**Draw the circuit diagram of voltage divider bias circuit using CE configuration and explain how it stabilizes the operating point.

**5.a.**$Y=ABC+BC'D+A'BC$ & realize using gates.

**5.b.**Explain parallel I/P serial output shift register.

**5.c.**Minimize the following expression using only one 8:1 MUX.

$\mathrm{F}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum \mathrm{m}(1,2,9,10,11,14,15)$

**Write a short notes on any four**

**6.a.**BCD & excess-3 codes.

**6.b.**Current mirror circuit.

**6.c.**Ring counter.

**6.d.**ALU.

**6.e.**Modelling styles in VHDL.

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