Question Paper: Logic Design Question Paper - Dec 18 - Information Technology (Semester 3) - Mumbai University (MU)
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Logic Design - Dec 18

Information Technology (Semester 3)

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

1.a. What are the important features of differential amplifier, also states its types.
(5 marks) 3126

1.b. State De'sMorgon theorem & implement OR gate using NAND gate only.
(5 marks) 1468

1.c. ADD $(83)_{10}$ & $(34)_{10}$ in BCD.
(5 marks) 1253

1.d. Convert S-R flip flop to D flip-flop.
(5 marks) 1806

1.e. State advantages & disadvantages of multiplexer.
(5 marks) 1507

1.f. Explain VHDL format in brief.
(5 marks) 1821

2.a. Simplify the following using Quine-Mcclusky method.
$\mathrm{F}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum \mathrm{m}(0,3,4,11,15)+\mathrm{d}(1,2,5)$
(10 marks) 00

2.b. Design & implement one digit BCD adder using IC 7483.
(10 marks) 00

3.a. Design MOD-11 ripple counter using suitable flip-flop.
(07 marks) 1805

3.b. Convert the following decimal number into binary, octal & hexadecimal.

  1. $(555)_{10}$ 2. $(138)_{10}$ 3. $(79)_{10}$
(09 marks) 1252

3.c. Why transistor biasing is required, state factors required for it .
(5 marks) 00

4.a. Draw truth table of full subtractor & realize using 3-8 decoder.
(10 marks) 1511

4.b. Draw the circuit diagram of voltage divider bias circuit using CE configuration and explain how it stabilizes the operating point.
(10 marks) 3125

5.a. $Y=ABC+BC'D+A'BC$ & realize using gates.
(6 marks) 1465

5.b. Explain parallel I/P serial output shift register.
(6 marks) 00

5.c. Minimize the following expression using only one 8:1 MUX.
$\mathrm{F}(\mathrm{A}, \mathrm{B}, \mathrm{C}, \mathrm{D})=\sum \mathrm{m}(1,2,9,10,11,14,15)$
(5 marks) 1512

Write a short notes on any four

6.a. BCD & excess-3 codes.
(5 marks) 1519

6.b. Current mirror circuit.
(5 marks) 00

6.c. Ring counter.
(5 marks) 1814

6.d. ALU.
(5 marks) 3105

6.e. Modelling styles in VHDL.
(5 marks) 00

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modified 5 weeks ago by gravatar for Yashbeer Yashbeer170 written 5 months ago by gravatar for shraddhasapte12 shraddhasapte120
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