Question Paper: Design With Linear Integrated Circuits Question Paper - May 17 - Electronics Engineering (Semester 5) - Mumbai University (MU)

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## Design With Linear Integrated Circuits - May 17

### Electronics Engineering (Semester 5)

Total marks: 80

Total time: 3 Hours
INSTRUCTIONS

(1) Question 1 is compulsory.

(2) Attempt any **three** from the remaining questions.

(3) Draw neat diagrams wherever necessary.

**1.a.**Compare integrator and differentiator.

**1.b.**Define input offset voltage, output offset voltage, input bias

**1.c.**Explain any five specifications of the digital to analog converter (DAC).

**1.d.**Describe the basic block diagram of the phase locked Loop (PLL).

**2.a.**Describe the expression of inverting & the non-inverting amplifier using op-amp (Av) & design them both for |AV|=10

**2.b.**Derive the output voltage $\left(\mathrm{V}_{0}\right)$ expression of ap-amp three input averaging circuit.

**3.a.**Design $2^{n d}$ order KRC Low pass filter (LPF) for cut-off frequency fo=10 kHz with quality factor (Q) of 5.

**3.b.**Design $1^{\mathrm{st}}$ order high pass filter for a cut-off frequency fo=2 kHz with unity gain. How will you modify the design to achieve low pass filter (LPF) operation?

**4.a.**Describe the parallel comparator/flash type analog to digital

**4.b.**Explain the operation of Schmitt Trigger with neat diagram, input & output waveforms with transfer characteristics.

**5.a.**Design a monostable multivibrator using IC 555 to generate a time delay of T=500ms. Assume $+\mathrm{V}_{\mathrm{cc}}=10 \mathrm{V}$

**4.b.**Design a positive voltage regulator to generate Vo =+5V with Io = 50mA by using IC LM 723. Draw neat diagram of the designed circuit.

**6.a.**3 stage R-C phase shift oscillator using op-amp.

**6.b.**Triangular waveform generator using op-amp.

**6.c.**Precision Rectifier using op-amp.

**6.d.**Log-Antilog amplifier using op-amp.

**6.d.**Voltage controlled oscillator (VCO)