Solve any five of the following

1.a. Determine the value of Rc such that Vc = 5V and β = 50

1.b. State and explain Miller's Theorem.

1.c. Design a self bias circuit using JFET for $\mathrm{I}_{\mathrm{D}}=3 \mathrm{mA}, \mathrm{V}_{\mathrm{DD}}=20 \mathrm{V}$ and $\mathrm{V}_{\mathrm{DS}}=0.6 \mathrm{V}_{\mathrm{DO}}$ $\left(\mathrm{I}_{\mathrm{DSS}}=8 \mathrm{mA}, \mathrm{V}_{\mathrm{P}}=-4 \mathrm{V}\right)$

1.d. Explain various types of capacitors.

1.e. Determine the values of coupling capacitors Cc1 and Cc2 if $\mathrm{r}_{\mathrm{I}}=1.5 \mathrm{K} \Omega, \beta=120$ and $\mathrm{f}_{\mathrm{L}}=20 \mathrm{Hz}$

1.f. Explain concept of zero temperature drift in JFET.

2.a. Calculate 1) $\mathrm{I}_{\mathrm{BQ}}, \mathrm{I}_{\mathrm{CQ}} \quad$ 2) $\mathrm{g}_{\mathrm{m}}, \mathrm{r}_{\mathrm{II}}$ 3) Small signal voltage gain

For the circuit below

2.b. Explain the concept of LC filter in power supply circuit and hence derive expression for ripple factor of LC Filter.

3.a. Explain concept of shunt Zener regulator. For a shunt Zener regulator giving output voltage of 10V and load resistance varying from 5KΩ to 10KΩ, Vin is varying between 18V to 22V.

Find Rs, Pzmax, Sv and Ro.

Assume Rz = 4Ω and Izmin = 50μA.

3.b. Determine $\mathrm{I}_{\mathrm{DQ}}, \mathrm{V}_{\mathrm{GSQ}}, \mathrm{V}_{\mathrm{DSQ}}$ if $\mathrm{I}_{\mathrm{DSS}}=9 \mathrm{mA}$ and $\mathrm{V}_{\mathrm{p}}=-3 \mathrm{V}$ for the circuit given below.

4.a. Design capacitive filter with FWR using two diodes with ripple factor less than 5%.

Output voltage is 24V and load current 200mA. The input line voltage of 230V/50Hz is available.

4.b. Determine the values of biasing components for a CE configuration if Vcc = 12V, $\mathrm{V}_{\mathrm{CE}}=6 \mathrm{V}, \mathrm{Rc}=1 \mathrm{K} \Omega, \mathrm{V}_{\mathrm{BE}}=0.6 \mathrm{V}, \beta=180$ β = 180 for the following circuit.

i. Fixed bias without

ii. Voltage Divider bias with = 10% of Vcc and S₁ = 8.

5.a. For JFET if $\mathrm{I}_{\mathrm{DSS}}=6 \mathrm{mA}, \mathrm{V}_{\mathrm{p}}=-6 \mathrm{V} \mathrm{rd}=\infty, \mathrm{Cgd}=4 \mathrm{pF}, \mathrm{Cgs}=6 \mathrm{pF}, \mathrm{Cds}=1 \mathrm{pF}$

Determine

iii. gmo    iv. gm

v. Midband voltage gain Av

vi. Higher cut off frequency

5.b. Explain high frequency equivalent model of common emitter BJT.

6. Design single stage CS amplifier using mid-point biasing method for voltage gain of 12,$\mathrm{F}_{\mathrm{L}}=20 \mathrm{Hz}, \mathrm{R}_{\mathrm{L}}=10 \mathrm{K} \Omega, \mathrm{Vo}=3.5 \mathrm{V}$

(Use JFET parameters $\mathrm{I}_{\mathrm{DSS}}=7 \mathrm{m} \mathrm{A}, \mathrm{V}_{\mathrm{P}}=-2.5 \mathrm{V}, \mathrm{gmo}=5600 \mu \mathrm{U}, \mathrm{rd}=50 \mathrm{K} \Omega )$)