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VLSI Design and Technology Question Paper - Dec 18 - Electronics And Telecomm (Semester 7) - Pune University (PU)
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VLSI Design and Technology - Dec 18
Electronics And Telecomm (Semester 7)
Total marks: 70
Total time: 2.30 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.
1.a.
Explain subprograms in detail.
(6 marks)
00
i) Functions and
ii) Procedures
1.b.
Write short note on clock distribution technique.
(7 marks)
00
1.c.
Draw CPLD XC9500 series architecture and explain in detail.
(7 marks)
00
OR
2.a.
Draw HDL design flow and explain in brief.
(6 marks)
00
2.b.
Explain clock skew and write in detail about positive and negative clock skew.
(7 marks)
00
2.c.
Draw and explain the architecture of FPGA XC4000 series with neat
diagram.
(7 marks)
00
3.a.
Explain CMOS inverter circuit with neat diagram and plot voltage transfer
characteristics.
(8 marks)
00
3.b.
Explain static and dynamic power dissipation analysis of CMOS inverter circuit.
(8 marks)
00
OR
4.a.
Explain in detail latch up effect, latch up prevention techniques and comment on system level approach to avoid latch ups.
(8 marks)
00
4.b.
Draw circuit diagram of transmission gate and explain in detail.
(8 marks)
00
5.a.
Write in detail lambda rules with diagram.
(10 marks)
00
5.b.
Explain cross talk in detail.
(8 marks)
00
OR
6.a.
Write in detail micron based design rules.
(10 marks)
00
6.b.
Write short note on Layout Vs Schematic and Explain LVS checking
process.
(8 marks)
00
7.a.
What is JTAG, explain in detail.
(8 marks)
00
7.b.
Explain Built in Self Test (BIST).
(8 marks)
00
OR
8.a.
Draw and explain architecture of TAP controller.
(8 marks)
00
8.b.
Describe types of faults? Explain with schematics.
(8 marks)
00
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