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Digital Electronics And Logic Design Question Paper - Jun 17 - Computer Engineering (Semester 3) - Pune University (PU)
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Digital Electronics And Logic Design - Jun 17

Computer Engineering (Semester 3)

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

1.a. implement the expression using 8 : 1 multiplexer f(a, b, c, d) = £m(0, 2, 3, 6, 8, 9, 12, 14).
(4 marks) 00

1.b. What is the difference between combinational and sequential circuit ?
(2 marks) 00

1.c. simplify the following logical function using the queen-McCluskey minimization technique: Y(A, B, C, D) = £m(1, 3, 7, 8, 9, 11, 15).
(6 marks) 00

Or

2.a Explain in detail look ahead carry generator
(6 marks) 00

2.b. Design mod-24 counter using 7490.
(2 marks) 00

2.c. Designe a sequence detector using MS J-K flip-flop sequence is 1101.
(4marks) 00

3.a. Draw ASM for 2-bit Up counter using multiplexer controller method.
(8 marks) 00

3.b. List any two medeling style of VHDL.
(2 marks) 00

3.c. Compare concurrent and sequential statement in VHDL.
(2 marks) 00

Or

4.a.<\b> Design 4 input and 6 output combinational circuit using PLA. The input variable are A, B, C and D. Y1 = £m(0, 3, 5, 6, 9, 10, 12, 15)

Y2 = £m(1, 2, 3, 11, 12, 14, 15)

Y3 = £m(0, 4, 8, 12)

Y4 = £m(0, 2, 3, 5, 7, 8, 12, 13)

Y5 = £m(0, 1, 3, 4, 5, 6, 11, 13, 14, 15)

Y5 = £m(1, 2, 6, 8, 15).

(6 marks) 00

4.b. Draw block diagram of PLA device and explain.
(6 marks) 00

5.a. explain characteristics of digital ICs (any four).
(4 marks) 00

5.b. Explain operation of TTL NAND gate.
(6 marks) 00

5.c. Explain TTL open collector.
(3 marks) 00

Or

6.a.What is addressing mode ? Identify and justify addressing mode of the following 8051 instruction : (i) MOVX A, @DPTR (ii) MOVC A, @ A+PC (iii) ADD A, #10 (iv) MOV DPTR, #2550.
(6 marks) 00

6.b. What is microcontroller? Distinguish between microcontroller and microprocessor.
(7 marks) 00

7.a. Explain CMOS inverter.
(4 marks) 00

7.b. Why wired logic is not possible in CMOS operation.
(4 marks) 00

7.c. Explain tristate logic.
(5 marks) 00

Or

8.a. Explain the physical structure and significances of I/O ports of 8051 microcontroller.

(7 marks) 00

8.b. Give significance of the following pins in 8051: (i) PSEN# (ii) EA#VPP (iii) ALE (iv) TxD (v) INT0# (vi) RST.
(6 marks) 00

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