Question Paper: Linear and Digital IC Applications Question Paper - Jun 16 - Electronics And Communication Engineering (Semester 5) - Jawaharlal Nehru Technological University (JNTUH)
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## Linear and Digital IC Applications - Jun 16

### Electronics And Communication Engineering (Semester 5)

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

PART - A

1.a. Assuming the OP-AMP to be ideal, the voltage gain of the amplifier shown below is (2 marks) 00

1.b. How does negative feedback compensate for a decrease in open loop gain?
(2 marks) 00

1.c. An astable multi vibrator circuit using IC 555 timer is shown below. Assume that the circuit is oscillating steadily, find the voltage $\mathrm{V}_{\mathrm{C}}$ across the capacitor varies between. (2 marks) 00

1.d. Calculate the values of the LSB, MSB and Full scale output for an 8-bit DAC for the 0 to 10V.
(2 marks) 00

1.e. The op-amp circuit shown in figure is a filter. The type of filter and it’s cutoff frequency respectively. (2 marks) 00

1.f. What is an all pass filter? Where and why it is needed?
(2 marks) 00

1.g. When do we prefer open collector TTL gate?
(2 marks) 00

1.h. Which is fastest logic gate and why?
(2 marks) 00

1.i. Why asynchronous inputs are required in flip-flops?
(2 marks) 00

(2 marks) 00

PART - B

UNIT - I

2.a. Derive an expression for the output voltage and gain of a non-inverting op-amp
(5 marks) 00

2.b. The output voltage of the regulated power supply shown in figure is: (5 marks) 00

OR

3.a. Show that input impedance of a non-inverting op-amp of figure below is: $R_{i f}=R_{i}\left(1+\frac{R_{1}}{\left(R_{1}+R_{2}\right)} A_{v}\right)$ . Where $R_{i}$ is input resistance of an op-amp and $A_{v}$ is open loop gain and output resistance $R_{0}=0$. (5 marks) 00

3.b. What is the purpose of sample and hold circuit? Explain the working principle of sample and hold circuit usingan op-amp.

(5 marks) 00

UNIT - II

4.a. Configure a 555 timer as a Schmitt trigger and explain. Mention some of its applications.

(5 marks) 00

4.b. The circuit shown is a 4-bit DAC the input bits 0 and 1 are represented by 0 V and 5 V respectively. The op-amp is ideal and all the resistances and the 5 V input have a tolerance of + or–10%. The specification(rounded to the nearest multiple of 5%) for the tolerance of the DAC is: (5 marks) 00

OR

5.a. Explain frequency translation and FSK demodulation using 565 PLL.
(5 marks) 00

5.b. An 8-bit ADC is capable of accepting an input unipolar (positive values only) voltage 0 to 10 V. Find what the minimum value of 1LSB is & what is the digital output code if the applied input voltage is 5.4V?

(5 marks) 00

UNIT - III

6.a. Derive an expression for the transfer function of a second order low pass Butterworth filter.
(5 marks) 00

6.b. Explain VCO? Mention applications of it.
(5 marks) 00

OR

7.a. Explain the terms: (i) Roll of factor. (ii) Damping coefficient.
(5 marks) 00

7.b. Explain,how to obtain triangular wave using a square wave generator?
(5 marks) 00

UNIT - IV

8.a. Differentiate different logic families and mention their advantages and disadvantages.
(5 marks) 00

8.b. Describe TTL driving CMOS and CMOS driving TTL, interfacing techniques.
(5 marks) 00

OR

9.a. Draw the circuit of Totem-pole TTL NAND gate. What is the purpose of using a diode at the output?
(5 marks) 00

9.b. Design a TTL three state NAND gate and explain the operation.
(5 marks) 00

UNIT - V

10.a. What is a decoder? Explain 3 to 8 line decoder with its truth table.
(5 marks) 00

10.b. Design a 3-bit binary synchronous counter.

(5 marks) 00

OR

11.a. What is parity generator? Explain the 3-bit even parity generator.
(5 marks) 00

11.b. Explain different types of shift registers.
(5 marks) 00

 modified 3 months ago  • written 3 months ago by shaikhainiya2001 • 0