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Digital Circuit Design Question Paper - Jun 19 - Electronics Engineering (Semester 3) - Mumbai University (MU)
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Digital Circuit Design - Jun 19

Electronics Engineering (Semester 3)

Total marks: 80
Total time: 3 Hours
INSTRUCTIONS
(1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Draw neat diagrams wherever necessary.

Attempt any four questions from the following.

$\mathbf{I}$ Compare TTL and CMOS Logic families with respect to i) Power dissipitation ii)Propogation delay iii)Figure of merit iv)Fan-out

(5 marks) 00

$\mathbf{II}$ Convert $(73.301)_{10}$ into binary, octal, Hexadecimal and BCD equivalent.
(5 marks) 00

$\mathbf{III}$ Simplify following three- variable expression using Boolean algebra $\prod M(0,1,3,4,7)$
(5 marks) 00

$\mathbf{IV}$ Design Half adder circuit using basic gate.
(5 marks) 00

$\mathbf{V}$ Explain different types of triggering methods used for flipflop
(5 marks) 00

2.a. Perform following operation: i) Addition $24 \mathrm{BCD}+18 \mathrm{BCD}$ ii) Subtraction $46_{10}-22_{10}$ using 2'a complement method
(10 marks) 00

2.b. Reduce the given expression and Realize using NAND gate only. Y = AB' + AC' + C + AD + AB'C + ABC
(10 marks) 00

3.a. ) Simplify the following function using Quine-Mc cluskey method. $\sum m(1,2,3,5,9,12,14,15)+\sum d(4,8,11)$
(10 marks) 00

3.b. Design 2 Bit Magnitude comparator using gates.
(10 marks) 00

4.a. Implement the following Boolean function with 8:1 Multiplexer F(A, B, C, D) = $\sum \mathrm{m}(0 2 6 10 11 12 13)+\sum \mathrm{d}(3 8 14)$
(10 marks) 00

4.b. Draw and explain working of Bidirectional shift register.
(10 marks) 00

5.a. Design MOD 13 Asynchronous up counter using JK Flip flop.
(10 marks) 00

5.b. Convert JK Flip Flop into D and SR flipflop
(10 marks) 00

6.a. Design 3 bit Synchronous counter using T flip flop.
(10 marks) 00

6.b. Explain Race around condition in JK flipflop and discuss solution to avoid Race around condition.
(10 marks) 00

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