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Logic Design Question Paper - Jun 19 - Information Technology (Semester 3) - Mumbai University (MU)

## Logic Design - Jun 19

### Information Technology (Semester 3)

Total marks: 80

Total time: 3 Hours
INSTRUCTIONS

(1) Question 1 is compulsory.

(2) Attempt any **three** from the remaining questions.

(3) Draw neat diagrams wherever necessary.

**1.a.**Explain DC operating point and its variation with the help of output characteristics of transistor.

**1.b.**Convert S-R flip flop to J-K flip flop.

**1.c.**Design Ex-OR gate using NAND and NOR gates.

**1.d.**Design full substractor using half substractor and additional gates.

**1.e.**Convert following decimal number to Binary ,Octal, Hexadecimal and Gray code

i) (345)10 ii)(818)10

**2.a.**Explain collector to base bias Circuit with its stability factor.

**2.b.**Minimize the following four variable logic function using K-map and Design using only NAND gates.

f(A,B,C,D)=∑m (0,1,2,3,5,8,9,10,11,12,14)

**3.a.**Design 4-bit binary to gray code conversion using basic gates.

**3.b.**1. Implement following using only one 8:1 Multiplexer and few gates. F(A,B,C,D)= ∑ m(1,3,4,5,8,9,12,15)

2.With neat logic diagram explain in short operation of Universal Shift Register.

**4.a.**Design a Mod 10 synchronous counter using J-K Flip-Flop.

**4.b.**Using Quine MC Cluskey Method determine Minimal SOP form for

F(A,B,C,D)= ∑ m(0,1,2,5,6,7,8,9,10,14)

**5.a.**Explain about ENTITY declarations in VHDL and write VHDL program for NAND and OR gates.

**5.b.**Implement 3 bit asynchronous u p counter and also sketch the timing diagram.

**6.a.**Solve the following Explain working of 8:1 Multiplexer.

**6.b.**Solve the following Working of S-R flip flop(with its internal circuit diagram and truth table).

**6.c.**Solve the following Explain working of Constant Current source.

**6.d.**Solve the following Write VHDL program for full substractor.

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